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mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU 

DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM
configuration.

TEST=Boot DDR5 MR SKU to OS.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56881
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Meera Ravindranath 2021-08-09 16:06:21 +05:30 committed by Nick Vaccaro
parent adc9e63c59
commit bcc74afa73
3 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/adlrvp/romstage_fsp_params.c
View File

@ -53,9 +53,9 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
case ADL_P_DDR5_1:
case ADL_P_DDR5_2:
memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated);
break;
case ADL_P_DDR5_2:
case ADL_P_LP4_1:
case ADL_P_LP4_2:
case ADL_P_LP5_1:

2
src/mainboard/intel/adlrvp/spd/Makefile.inc
View File

@ -6,5 +6,5 @@ SPD_SOURCES += adlrvp_m_lp5 # 0b002
SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
SPD_SOURCES += empty # 0b006
SPD_SOURCES += adlrvp_ddr5_mr # 0b006
SPD_SOURCES += adlrvp_lp5 # 0b007

32
src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex Normal file
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@ -0,0 +1,32 @@
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