security/intel/txt/ramstage.c: Fix clearing secrets on CBNT
intel_txt_memory_has_secret() checks for ESTS.TXT_ESTS_WAKE_ERROR_STS || E2STS.TXT_E2STS_SECRET_STS and it looks like with CBNT the E2STS bit can be set without the ESTS bit. Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47934 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -89,23 +89,21 @@ static void check_secrets_txt(void *unused)
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if (status & ACMSTS_TXT_DISABLED)
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return;
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/* Check for fatal ACM error and TXT reset */
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if (get_wake_error_status()) {
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/*
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* Check if secrets bit needs to be reset. Only platforms that support
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* CONFIG(PLATFORM_HAS_DRAM_CLEAR) will be able to run this code.
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* Assume all memory really was cleared.
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*
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* TXT will issue a platform reset to come up sober.
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*/
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if (intel_txt_memory_has_secrets()) {
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printk(BIOS_INFO, "TEE-TXT: Wiping TEE...\n");
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intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS);
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/*
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* Check if secrets bit needs to be reset. Only platforms that support
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* CONFIG(PLATFORM_HAS_DRAM_CLEAR) will be able to run this code.
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* On some platforms FSP-M takes care of the DRAM clearing.
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* Assume all memory really was cleared.
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*
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* TXT will issue a platform reset to come up sober.
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*/
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if (intel_txt_memory_has_secrets()) {
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printk(BIOS_INFO, "TEE-TXT: Wiping TEE...\n");
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intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS);
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/* Should never reach this point ... */
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intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE));
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die("Waiting for platform reset...\n");
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}
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/* Should never reach this point ... */
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intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE));
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die("Waiting for platform reset...\n");
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}
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}
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