From bcd0bdabedb2b99d670afff4ef516535f66c2dbb Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Fri, 15 Sep 2017 12:33:24 -0600
Subject: [PATCH] soc/intel/cannonlake: add rtc failure checking

In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred. In addition actually
provide soc_get_rtc_failed() which properly indicates to the common
code that RTC failure did occur in the cmos_init() path.

BUG=b:63054105

Change-Id: I9dcb9377c758b226ee7bcc572caf11b7b2095425
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/cannonlake/pmutil.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 6708781fa5..ebd3d61cc8 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -22,11 +22,13 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <cbmem.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
 #include <halt.h>
 #include <rules.h>
 #include <stdlib.h>
@@ -188,3 +190,20 @@ void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 	*dw1 = config->gpe0_dw1;
 	*dw2 = config->gpe0_dw2;
 }
+
+static int rtc_failed(uint32_t gen_pmcon_b)
+{
+	return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
+}
+
+int soc_get_rtc_failed(void)
+{
+	const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+	if (!ps) {
+		printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");
+		return 1;
+	}
+
+	return rtc_failed(ps->gen_pmcon_b);
+}