mainboard: Use decimal for device domain 0x0 on
Most boards use `device domain 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
parent
d2489ee712
commit
bceea67461
25 changed files with 25 additions and 25 deletions
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@ -23,7 +23,7 @@ chip northbridge/intel/sandybridge
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "docking_supported" = "0"
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@ -22,7 +22,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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device pci 00.0 on
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device pci 00.0 on
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subsystemid 0x1849 0x0150
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subsystemid 0x1849 0x0150
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end
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end
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@ -10,7 +10,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x1043 0x844d inherit
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subsystemid 0x1043 0x844d inherit
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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@ -10,7 +10,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1)
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device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1)
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device pci 02.0 on end # Internal graphics VGA controller
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device pci 02.0 on end # Internal graphics VGA controller
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@ -10,7 +10,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x1043 0x84ca inherit
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subsystemid 0x1043 0x84ca inherit
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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@ -15,7 +15,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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device pci 00.0 on # Host bridge
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device pci 00.0 on # Host bridge
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subsystemid 0x8086 0x2010
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subsystemid 0x8086 0x2010
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end
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end
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@ -9,7 +9,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x1028 0x052c inherit
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subsystemid 0x1028 0x052c inherit
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device pci 00.0 on end # Host bridge Host bridge
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device pci 00.0 on end # Host bridge Host bridge
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@ -16,7 +16,7 @@ chip northbridge/intel/sandybridge
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x1495 inherit
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subsystemid 0x103c 0x1495 inherit
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device pci 00.0 on end # Host bridge Host bridge
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device pci 00.0 on end # Host bridge Host bridge
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@ -19,7 +19,7 @@ chip northbridge/intel/haswell
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x22da inherit
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subsystemid 0x103c 0x22da inherit
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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device pci 02.0 on end # Internal graphics VGA controller
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device pci 02.0 on end # Internal graphics VGA controller
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@ -24,7 +24,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x00000437"
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register "gpu_cpu_backlight" = "0x00000437"
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register "gpu_panel_power_backlight_off_delay" = "2300"
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register "gpu_panel_power_backlight_off_delay" = "2300"
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register "gpu_pch_backlight" = "0x0d9c0d9c"
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register "gpu_pch_backlight" = "0x0d9c0d9c"
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x17df inherit
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subsystemid 0x103c 0x17df inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x00000129"
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register "gpu_cpu_backlight" = "0x00000129"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_pch_backlight" = "0x02880288"
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register "gpu_pch_backlight" = "0x02880288"
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x162a inherit
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subsystemid 0x103c 0x162a inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x00000129"
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register "gpu_cpu_backlight" = "0x00000129"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_pch_backlight" = "0x02880288"
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register "gpu_pch_backlight" = "0x02880288"
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x161c inherit
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subsystemid 0x103c 0x161c inherit
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x00000385"
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register "gpu_cpu_backlight" = "0x00000385"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_pch_backlight" = "0x0d9c0d9c"
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register "gpu_pch_backlight" = "0x0d9c0d9c"
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x179b inherit
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subsystemid 0x103c 0x179b inherit
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/sandybridge
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chip northbridge/intel/sandybridge
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x176c inherit
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subsystemid 0x103c 0x176c inherit
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device pci 01.0 on # PCIe Bridge for discrete graphics
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device pci 01.0 on # PCIe Bridge for discrete graphics
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@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x00000d9c"
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register "gpu_cpu_backlight" = "0x00000d9c"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_pch_backlight" = "0x0d9c0d9c"
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register "gpu_pch_backlight" = "0x0d9c0d9c"
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x18df inherit
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subsystemid 0x103c 0x18df inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x00000263"
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register "gpu_cpu_backlight" = "0x00000263"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_pch_backlight" = "0x02880288"
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register "gpu_pch_backlight" = "0x02880288"
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x18f8 inherit
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subsystemid 0x103c 0x18f8 inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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@ -16,7 +16,7 @@ chip northbridge/intel/sandybridge
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x103c 0x1791 inherit
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subsystemid 0x103c 0x1791 inherit
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device pci 00.0 on end # Host bridge Host bridge
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device pci 00.0 on end # Host bridge Host bridge
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@ -22,7 +22,7 @@ chip northbridge/intel/sandybridge
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register "acpi_c3" = "5"
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register "acpi_c3" = "5"
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics VGA controller
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device pci 02.0 on end # Internal graphics VGA controller
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@ -20,7 +20,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x17aa 0x2205 inherit
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subsystemid 0x17aa 0x2205 inherit
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device pci 00.0 on end # Host bridge Host bridge
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device pci 00.0 on end # Host bridge Host bridge
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@ -24,7 +24,7 @@ chip northbridge/intel/sandybridge
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x17aa 0x21f3 inherit
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subsystemid 0x17aa 0x21f3 inherit
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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@ -19,7 +19,7 @@ chip northbridge/intel/haswell
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x17aa 0x220e inherit
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subsystemid 0x17aa 0x220e inherit
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device pci 00.0 on end # Host bridge Host bridge
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device pci 00.0 on end # Host bridge Host bridge
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@ -26,7 +26,7 @@ chip northbridge/intel/sandybridge
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x17aa 0x21fe inherit
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subsystemid 0x17aa 0x21fe inherit
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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@ -8,7 +8,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x1462 0x7707 inherit
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subsystemid 0x1462 0x7707 inherit
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device pci 00.0 on end # Host bridge
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device pci 00.0 on end # Host bridge
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@ -10,7 +10,7 @@ chip northbridge/intel/sandybridge
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device lapic 0xacac off end
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device lapic 0xacac off end
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "c2_latency" = "0x0065"
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register "gen1_dec" = "0x000c0291"
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register "gen1_dec" = "0x000c0291"
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