mainboard/google/coral: Add USB2 phy setting override for Santa
In order to pass type C USB2 eye diagram for sku Santa, USB2 port#1 PHY register needs to be overridden. port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 BUG=b:64880573 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -16,6 +16,13 @@
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#include <stdint.h>
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#include <ec/google/chromeec/ec.h>
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#include "baseboard/variants.h"
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#include <soc/cpu.h>
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#include <soc/intel/apollolake/chip.h>
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enum {
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SKU_2_SANTA = 2,
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SKU_3_SANTA = 3
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};
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uint8_t variant_board_sku(void)
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{
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@ -31,3 +38,22 @@ void variant_nhlt_oem_overrides(const char **oem_id,
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*oem_table_id = CONFIG_VARIANT_DIR;
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*oem_revision = variant_board_sku();
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}
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void mainboard_devtree_update(struct device *dev)
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{
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/* Override dev tree settings per board */
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struct soc_intel_apollolake_config *cfg = dev->chip_info;
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uint8_t sku_id;
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sku_id = variant_board_sku();
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switch (sku_id) {
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case SKU_2_SANTA:
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case SKU_3_SANTA:
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cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7;
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cfg->usb2eye[1].Usb20PerPortTxiSet = 2;
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break;
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default:
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break;
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}
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}
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