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intel/e7505: Remove commented out suspicious code 

Change-Id: I566f016eb4fb710a5246be8b088ab0d2ed00041c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38294
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-01-07 11:16:35 +02:00
parent d1141ab5a4
commit bd077cb396
1 changed files with 0 additions and 26 deletions
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26
src/northbridge/intel/e7505/raminit.c
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@ -1257,21 +1257,6 @@ static void configure_e7501_dram_controller_mode(const struct
refresh_frequency[system_refresh_mode])
system_refresh_mode = dimm_refresh_mode;
#ifdef SUSPICIOUS_LOOKING_CODE
// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
// than the clock period of the memory controller. Also, no other northbridge
// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
// Switch to 2 clocks for address/command if required by any one of the DIMMs
// NOTE: At 133 MHz, 1 clock == 7.52 ns
value = smbus_read_byte(dimm_socket_address,
SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
die_on_spd_error(value);
if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
controller_mode &= ~(1 << 16); /* Use two clock cycles instead of one */
}
#endif
/* go to the next DIMM */
}
@ -1724,17 +1709,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
byte &= ~0x60;
pci_write_config8(MCHDEV, 0xd9, byte);
#ifdef SUSPICIOUS_LOOKING_CODE
/* This will access D2:F0:0x50, is this correct??
* Vendor BIOS reads Device ID before this is set.
* Undocumented in the p64h2 PCI-X bridge datasheet.
*/
byte = pci_read_config8(PCI_DEV(0,2,0), 0x50);
byte &= 0xcf;
byte |= 0x30
pci_write_config8(PCI_DEV(0,2,0), 0x50, byte);
#endif
uint8_t revision = pci_read_config8(MCHDEV, 0x08);
if (revision >= 3)
d060_control(D060_CMD_1);