intel/e7505: Remove commented out suspicious code
Change-Id: I566f016eb4fb710a5246be8b088ab0d2ed00041c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38294 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1257,21 +1257,6 @@ static void configure_e7501_dram_controller_mode(const struct
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refresh_frequency[system_refresh_mode])
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refresh_frequency[system_refresh_mode])
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system_refresh_mode = dimm_refresh_mode;
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system_refresh_mode = dimm_refresh_mode;
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#ifdef SUSPICIOUS_LOOKING_CODE
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// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
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// than the clock period of the memory controller. Also, no other northbridge
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// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
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// Switch to 2 clocks for address/command if required by any one of the DIMMs
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// NOTE: At 133 MHz, 1 clock == 7.52 ns
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value = smbus_read_byte(dimm_socket_address,
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SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
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die_on_spd_error(value);
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if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
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controller_mode &= ~(1 << 16); /* Use two clock cycles instead of one */
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}
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#endif
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/* go to the next DIMM */
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/* go to the next DIMM */
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}
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}
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@ -1724,17 +1709,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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byte &= ~0x60;
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byte &= ~0x60;
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pci_write_config8(MCHDEV, 0xd9, byte);
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pci_write_config8(MCHDEV, 0xd9, byte);
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#ifdef SUSPICIOUS_LOOKING_CODE
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/* This will access D2:F0:0x50, is this correct??
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* Vendor BIOS reads Device ID before this is set.
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* Undocumented in the p64h2 PCI-X bridge datasheet.
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*/
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byte = pci_read_config8(PCI_DEV(0,2,0), 0x50);
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byte &= 0xcf;
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byte |= 0x30
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pci_write_config8(PCI_DEV(0,2,0), 0x50, byte);
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#endif
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uint8_t revision = pci_read_config8(MCHDEV, 0x08);
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uint8_t revision = pci_read_config8(MCHDEV, 0x08);
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if (revision >= 3)
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if (revision >= 3)
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d060_control(D060_CMD_1);
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d060_control(D060_CMD_1);
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