sdm845: Add QCLib to RomStage to perform IP init
CB acts as I/O handler for QCLib (e.g. DDR training data) This interface allows bi-directional data flow between CB and QCLib Tested and working interfaces: DDR Training data QCLib serial console output DDR Information (base & size) limits cfg data TEST=build & run Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
T Michael Turney
Julius Werner
parent
101098c41a
commit
bd0b51c0be
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@ -24,16 +24,15 @@ FLASH@0x0 8M {
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RO_FRID 0x100
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}
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RO_VPD(PRESERVE) 16K
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# TODO(hungte): Remove RO_PRESERVE.
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RO_PRESERVE(PRESERVE) {
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RO_DDR_TRAINING 8K
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RO_FSG
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}
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RO_DDR_TRAINING(PRESERVE) 8K
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RO_LIMITS_CFG(PRESERVE) 4K
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RO_FSG(PRESERVE)
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}
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RW_VPD(PRESERVE) 32K
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RW_NVRAM(PRESERVE) 16K
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RW_DDR_TRAINING 8K
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RW_DDR_TRAINING(PRESERVE) 8K
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RW_LIMITS_CFG(PRESERVE) 4K
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 4K {
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SHARED_DATA
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@ -15,6 +15,7 @@
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#include <arch/stages.h>
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#include <soc/usb.h>
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#include <soc/qclib_common.h>
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static void prepare_usb(void)
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{
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@ -28,4 +29,7 @@ static void prepare_usb(void)
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void platform_romstage_main(void)
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{
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prepare_usb();
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/* QCLib: DDR init & train */
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qclib_load_and_run();
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}
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@ -25,6 +25,10 @@ romstage-y += gpio.c
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romstage-y += clock.c
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romstage-$(CONFIG_SDM845_QSPI) += qspi.c
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romstage-y += usb.c
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romstage-y += ../common/qclib.c
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romstage-y += qclib.c
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romstage-y += ../common/mmu.c
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romstage-y += mmu.c
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################################################################################
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ramstage-y += soc.c
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@ -39,6 +43,7 @@ ramstage-y += usb.c
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################################################################################
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CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include
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CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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@printf "Generating: $(subst $(obj)/,,$(@))\n"
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@ -28,11 +28,12 @@ SECTIONS
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{
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SSRAM_START(0x14680000)
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OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K)
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DMA_COHERENT(0x14699000, 0x2000)
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DMA_COHERENT(0x14699000, 8K)
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REGION(qcsdi, 0x146AC000, 44K, 4K)
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SSRAM_END(0x146C0000)
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BSRAM_START(0x14800000)
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REGION(fw_reserved2, 0x14800000, 0x16000, 4096)
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REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000)
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BOOTBLOCK(0x14816000, 40K)
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TTB(0x14820000, 56K)
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VBOOT2_WORK(0x1482E000, 12K)
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@ -40,15 +41,19 @@ SECTIONS
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TIMESTAMP(0x14836000, 1K)
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PRERAM_CBMEM_CONSOLE(0x14836400, 32K)
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PRERAM_CBFS_CACHE(0x1483E400, 70K)
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REGION(bsram_unused, 0x1484FC00, 0xA2400, 0x100)
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REGION(qclib, 0x148F2000, 0x80000, 4096)
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REGION(dcb, 0x14972000, 0x4000, 4096)
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REGION(pmic, 0x14976000, 0xA000, 4096)
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REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100)
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REGION(ddr_information, 0x148EDF00, 256, 256)
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REGION(limits_cfg, 0x148EE000, 4K, 4K)
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REGION(qclib_serial_log, 0x148EF000, 4K, 4K)
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REGION(ddr_training, 0x148F0000, 8K, 4K)
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REGION(qclib, 0x148F2000, 512K, 4K)
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REGION(dcb, 0x14972000, 16K, 4K)
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REGION(pmic, 0x14976000, 40K, 4K)
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BSRAM_END(0x14980000)
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DRAM_START(0x80000000)
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/* Various hardware/software subsystems make use of this area */
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REGION(dram_reserved, 0x85000000, 0x1A800000, 4096)
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REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000)
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POSTRAM_CBFS_CACHE(0x9F800000, 384K)
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RAMSTAGE(0x9F860000, 128K)
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RAMSTAGE(0x9F860000, 2M)
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}
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@ -16,8 +16,6 @@
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#ifndef _SOC_QUALCOMM_SDM845_MMU_H__
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#define _SOC_QUALCOMM_SDM845_MMU_H__
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#define DRAMSIZE4GB 0x100000000
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void sdm845_mmu_init(void);
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#endif // _SOC_QUALCOMM_SDM845_MMU_H_
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@ -17,10 +17,12 @@
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#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_
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#include <symbols.h>
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#include <types.h>
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DECLARE_REGION(ssram)
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DECLARE_REGION(bsram)
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DECLARE_REGION(dram_reserved)
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DECLARE_REGION(dcb);
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DECLARE_REGION(pmic);
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DECLARE_REGION(limits_cfg);
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#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_
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@ -17,12 +17,9 @@
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#include <arch/mmu.h>
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#include <arch/cache.h>
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#include <soc/mmu.h>
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#include <soc/mmu_common.h>
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#include <soc/symbols.h>
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#define CACHED_RAM (MA_MEM | MA_S | MA_RW)
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#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC)
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#define DEV_MEM (MA_DEV | MA_S | MA_RW)
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void sdm845_mmu_init(void)
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{
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mmu_init();
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@ -0,0 +1,50 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbfs.h>
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#include <fmap.h>
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#include <console/console.h>
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#include <soc/symbols.h>
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#include <soc/qclib_common.h>
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int qclib_soc_blob_load(void)
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{
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size_t size;
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ssize_t ssize;
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/* Attempt to load PMICCFG Blob */
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size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
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_pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW);
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if (!size)
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return -1;
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qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0);
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/* Attempt to load DCB Blob */
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size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb",
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_dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW);
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if (!size)
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return -1;
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qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0);
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/* Attempt to load Limits Config Blob */
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ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg,
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REGION_SIZE(limits_cfg));
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if (ssize < 0)
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return -1;
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qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA,
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_limits_cfg, ssize, 0);
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return 0;
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}
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@ -16,11 +16,13 @@
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#include <symbols.h>
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#include <device/device.h>
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#include <soc/mmu.h>
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#include <soc/mmu_common.h>
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#include <soc/symbols.h>
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static void soc_read_resources(struct device *dev)
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{
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ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB);
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ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB,
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ddr_region->size / KiB);
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reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB,
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REGION_SIZE(dram_reserved) / KiB);
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}
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