vendorcode/mediatek/mt8192: Fix set but unused variables

TEST: BUILD_TIMELESS=1 binary remains the same.

Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2023-04-18 19:53:22 +02:00 committed by Lean Sheng Tan
parent a9737abf78
commit bd429063d9
6 changed files with 6 additions and 23 deletions

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@ -1260,12 +1260,10 @@ void DVS_DMY_RD_EXIT(DRAMC_CTX_T *p)
void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable)
{
U32 val, fld;
U32 fld;
fld = Fld(1, (Fld_shft(u4Field) + u1ShuIdx));
val = (u1Enable) ? 1 : 0;
vIO32WriteFldAlign_All(u4Reg, u1Enable, fld);
}
@ -2218,4 +2216,3 @@ void ShuffleDfsToFSP1(DRAMC_CTX_T *p)
cbt_switch_freq(p, CBT_HIGH_FREQ);
}
}

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@ -296,20 +296,10 @@ static void SetDramInfoToConf(DRAMC_CTX_T *p)
void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p)
{
#if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
EMI_SETTINGS *emi_set;
U16 u2HighestFreq = u2DFSGetHighestFreq(p);
DRAM_PLL_FREQ_SEL_T highestfreqsel = 0;
U8 u1ShuffleIdx = 0;
#if (!__ETT__)//preloader
if(emi_setting_index == -1)
emi_set = &default_emi_setting;
else
emi_set = &emi_settings[emi_setting_index];
#else//ett
emi_set = &default_emi_setting;
#endif
// lookup table to find highest freq
highestfreqsel = GetSelByFreq(p, u2HighestFreq);
for (u1ShuffleIdx = DRAM_DFS_SHUFFLE_1; u1ShuffleIdx < DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++)

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@ -413,10 +413,8 @@ void switch_dramc_voltage_to_auto_mode(void)
#ifdef COMBO_MCP
static int mt_get_mdl_number(void)
{
static int found = 0;
static int mdl_number = -1;
found = 1;
mdl_number = get_ddr_geometry();
return mdl_number;
@ -1195,4 +1193,3 @@ unsigned int get_mr8_by_mrr(U8 channel, U8 rank)
return (mr8_value & 0xff);
}
#endif

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@ -585,9 +585,6 @@ void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK])
unsigned long long ch0_rank0_size, ch0_rank1_size;
unsigned long long ch1_rank0_size, ch1_rank1_size;
unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH);
unsigned long long dq_width;
dq_width = 2;
dram_rank_size[0] = 0;
dram_rank_size[1] = 0;

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@ -55,7 +55,7 @@
#if CALIBRATION_LOG
#define msg(_x_...) { print(_x_); }
#define msg2(_x_...) // { print(_x_); }
#define msg2(_x_...) { if (0) { print(_x_); } }
#define err(_x_...) { print(_x_); }
#else
#define msg(_x_...)
@ -65,10 +65,10 @@
#define info(_x_...) msg(_x_)
#define msg3(_x_...) // { print(_x_); }
#define msg3(_x_...) { if (0) { print(_x_); } }
#define msg4(_x_...)
#define msg5(_x_...)
#define jv_msg(_x_...)
#define jv_msg(_x_...) { if (0) { print(_x_); } }
#if EYESCAN_LOG
#define eye_msg(_x_...) { print(_x_); }
#else

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@ -65,6 +65,7 @@ extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32);
UINT16 upk = 1; \
INT32 msk = (INT32)(list); \
{ upk = 0; \
(void)upk; \
((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \
} \
}/*lint -restore */
@ -80,6 +81,7 @@ extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32);
UINT16 upk = 1; \
INT32 msk = (INT32)(list); \
{ upk = 0; \
(void)upk; \
((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \
} \
}/*lint -restore */