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cpu/amd: Correct number of MCA banks cleared 

Use the value discovered in the MCG_CAP[Count] for the number of MCA
status registers to clear.  The generations should have the following
number of banks:
 * Family 10h: 6 banks
 * Family 12h: 6
 * Family 14h: 6
 * Family 15h: 7
 * Family 16h: 6

Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2018-08-07 07:27:57 -06:00 committed by Martin Roth
parent e13dd172b1
commit bd4a3f8cd9
12 changed files with 45 additions and 9 deletions
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7
src/cpu/amd/agesa/family12/model_12_init.c
View File

@ -27,6 +27,8 @@
#include <cpu/amd/multicore.h> #include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam12.h> #include <cpu/amd/amdfam12.h>
#define MCG_CAP 0x179
# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x401 #define MC0_STATUS 0x401
static void model_12_init(struct device *dev) static void model_12_init(struct device *dev)
@ -35,6 +37,7 @@ static void model_12_init(struct device *dev)
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings; u32 siblings;
@ -52,9 +55,11 @@ static void model_12_init(struct device *dev)
disable_cache(); disable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 5; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
enable_cache(); enable_cache();

7
src/cpu/amd/agesa/family14/model_14_init.c
View File

@ -28,12 +28,15 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#define MCG_CAP 0x179
# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x401 #define MC0_STATUS 0x401
static void model_14_init(struct device *dev) static void model_14_init(struct device *dev)
{ {
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
int msrno; int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings; u32 siblings;
@ -75,9 +78,11 @@ static void model_14_init(struct device *dev)
x86_enable_cache(); x86_enable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

5
src/cpu/amd/agesa/family15tn/model_15_init.c
View File

@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
int msrno; int msrno;
unsigned int cpu_idx; unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
@ -72,9 +73,11 @@ static void model_15_init(struct device *dev)
x86_enable_cache(); x86_enable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

5
src/cpu/amd/agesa/family16kb/model_16_init.c
View File

@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
int msrno; int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings; u32 siblings;
@ -70,9 +71,11 @@ static void model_16_init(struct device *dev)
x86_enable_cache(); x86_enable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

5
src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View File

@ -62,6 +62,7 @@ static void model_10xxx_init(struct device *dev)
{ {
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
struct node_core_id id; struct node_core_id id;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings; u32 siblings;
@ -109,9 +110,11 @@ static void model_10xxx_init(struct device *dev)
disable_cache(); disable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 5; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
enable_cache(); enable_cache();

5
src/cpu/amd/pi/00630F01/model_15_init.c
View File

@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
int msrno; int msrno;
unsigned int cpu_idx; unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
@ -69,9 +70,11 @@ static void model_15_init(struct device *dev)
x86_enable_cache(); x86_enable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

5
src/cpu/amd/pi/00660F01/model_15_init.c
View File

@ -51,6 +51,7 @@ static void model_15_init(struct device *dev)
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
int msrno; int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings; u32 siblings;
@ -81,9 +82,11 @@ static void model_15_init(struct device *dev)
x86_enable_cache(); x86_enable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

5
src/cpu/amd/pi/00730F01/model_16_init.c
View File

@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
u8 i; u8 i;
msr_t msr; msr_t msr;
int num_banks;
int msrno; int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings; u32 siblings;
@ -66,9 +67,11 @@ static void model_16_init(struct device *dev)
x86_enable_cache(); x86_enable_cache();
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

2
src/include/cpu/amd/amdfam15.h
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@ -16,6 +16,8 @@
#ifndef CPU_AMD_FAM15_H #ifndef CPU_AMD_FAM15_H
#define CPU_AMD_FAM15_H #define CPU_AMD_FAM15_H
#define MCG_CAP 0x00000179
# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x00000401 #define MC0_STATUS 0x00000401
#define MSR_SMM_BASE 0xC0010111 #define MSR_SMM_BASE 0xC0010111
#define MSR_TSEG_BASE 0xC0010112 #define MSR_TSEG_BASE 0xC0010112

2
src/include/cpu/amd/amdfam16.h
View File

@ -16,6 +16,8 @@
#ifndef CPU_AMD_FAM16_H #ifndef CPU_AMD_FAM16_H
#define CPU_AMD_FAM16_H #define CPU_AMD_FAM16_H
#define MCG_CAP 0x00000179
# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x00000401 #define MC0_STATUS 0x00000401
#define HWCR_MSR 0xC0010015 #define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f #define NB_CFG_MSR 0xC001001f

1
src/northbridge/amd/amdmct/amddefs.h
View File

@ -128,6 +128,7 @@
#define CPUID_MODEL 1 #define CPUID_MODEL 1
#define MCG_CAP 0x00000179 #define MCG_CAP 0x00000179
#define MCG_CTL_P 8 #define MCG_CTL_P 8
#define MCA_BANKS_MASK 0xff
#define MC0_CTL 0x00000400 #define MC0_CTL 0x00000400
#define MC0_STA (MC0_CTL + 1) #define MC0_STA (MC0_CTL + 1)
#define MC4_MISC0 0x00000413 #define MC4_MISC0 0x00000413

5
src/soc/amd/stoneyridge/cpu.c
View File

@ -121,11 +121,14 @@ static void model_15_init(struct device *dev)
int i; int i;
msr_t msr; msr_t msr;
int num_banks;
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0 ; i < 6 ; i++) for (i = 0 ; i < num_banks ; i++)
wrmsr(MC0_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
setup_lapic(); setup_lapic();