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src/soc/intel/braswell/southcluster.c: Config i8254 timer 

ISA timer is not configured.
Add call setup_i8254().

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: If45c4975d147f28a456198ea290efba1c8b0464b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Frans Hendriks 2018-12-05 15:24:48 +01:00 committed by Patrick Georgi
parent 4f4322dd68
commit bd5233eb3d
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/braswell/southcluster.c
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@ -4,6 +4,7 @@
* Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc. * Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp. * Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -25,6 +26,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <pc80/i8254.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/iomap.h> #include <soc/iomap.h>
@ -182,6 +184,8 @@ static void sc_init(struct device *dev)
read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
} }
/* Initialize i8254 timers */
setup_i8254();
} }
/* /*