soc/intel/common: Add functions into common system agent library

This patch to add helper functions for memory layout design
based on PCI Host Bridge/DRAM registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.

Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/common/block/include/intelblocks/systemagent.h

@@ -73,7 +73,14 @@ void enable_bios_reset_cpl(void);
 void enable_pam_region(void);
 /* API to enable Power Aware Interrupt Routing through MCHBAR */
 void enable_power_aware_intr(void);
-
+/* API to get TOLUD base address */
+uint32_t sa_get_tolud_base(void);
+/* API to get DSM size */
+size_t sa_get_dsm_size(void);
+/* API to get GSM size */
+size_t sa_get_gsm_size(void);
+/* API to get DPR size */
+size_t sa_get_dpr_size(void);
 /*
  * SoC overrides
  *

src/soc/intel/common/block/systemagent/systemagent.c

@@ -99,26 +99,6 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
 		sa_read_map_entry(dev, &sa_memory_map[i], &values[i]);
 }
 
-/*
- * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC.
- */
-static size_t get_dpr_size(void)
-{
-	uintptr_t dpr_reg;
-	size_t size = 0;
-	/*
-	 * DMA Protected Range can be reserved below TSEG for PCODE patch
-	 * or TXT/BootGuard related data.  Rather than report a base address
-	 * the DPR register reports the TOP of the region, which is the same
-	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
-	 */
-	dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);
-	if (dpr_reg & DPR_EPM)
-		size = (dpr_reg & DPR_SIZE_MASK) << 16;
-
-	return size;
-}
-
 /*
  * These are the host memory ranges that should be added:
  * - 0 -> 0xa0000: cacheable
@@ -159,7 +139,7 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
 	int index = *resource_count;
 
 	if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
-		dpr_size = get_dpr_size();
+		dpr_size = sa_get_dpr_size();
 
 	top_of_ram = (uintptr_t)cbmem_top();
 

src/soc/intel/common/block/systemagent/systemagent_def.h

@@ -19,6 +19,12 @@
 
 /* Device 0:0.0 PCI configuration space */
 
+/* GMCH Graphics Comntrol Register */
+#define GGC		0x50
+#define  G_GMS_OFFSET	0x8
+#define  G_GMS_MASK	0xff00
+#define  G_GGMS_OFFSET	0x6
+#define  G_GGMS_MASK	0xc0
 /* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */
 #define DPR		0x5c
 #define  DPR_EPM	(1 << 2)

src/soc/intel/common/block/systemagent/systemagent_early.c

@@ -132,3 +132,55 @@ void enable_bios_reset_cpl(void)
 	bios_reset_cpl |= 3;
 	MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
 }
+
+uint32_t sa_get_tolud_base(void)
+{
+	/* All regions concerned for have 1 MiB alignment. */
+	return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB);
+}
+
+static uint16_t sa_get_ggc_reg(void)
+{
+	return pci_read_config16(SA_DEV_ROOT, GGC);
+}
+
+size_t sa_get_dsm_size(void)
+{
+	return (((sa_get_ggc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB);
+}
+
+size_t sa_get_gsm_size(void)
+{
+	uint8_t ggms;
+
+	ggms = (sa_get_ggc_reg() & G_GGMS_MASK) >> G_GGMS_OFFSET;
+
+	/*
+	 * Size of GSM: 0x0: No Preallocated Memory 0x1: 2MB Memory
+	 * 0x2: 4MB Memory 0x3: 8MB Memory
+	 */
+	if (ggms)
+		return 1*MiB << ggms;
+	else
+		return 0;
+}
+
+/*
+ * Get DPR size in case CONFIG_SA_ENABLE_DPR is selected by SoC.
+ */
+size_t sa_get_dpr_size(void)
+{
+	uintptr_t dpr_reg;
+	size_t size = 0;
+	/*
+	 * DMA Protected Range can be reserved below TSEG for PCODE patch
+	 * or TXT/BootGuard related data.  Rather than report a base address
+	 * the DPR register reports the TOP of the region, which is the same
+	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
+	 */
+	dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);
+	if (dpr_reg & DPR_EPM)
+		size = (dpr_reg & DPR_SIZE_MASK) << 16;
+
+	return size;
+}