From bd6deb9f735264e077d566a7403b68c612f8926c Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Mon, 6 Mar 2023 17:47:54 -0700
Subject: [PATCH] soc/amd/common/psp: Check more error bits before SPL fusing

This adds checks for three more error bits before requesting that the
SPL fuses are updated.

- While I'm here, I'm adding the include of types.h which was previously
done through other include files, but should be done independently.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I87a7d40850c4e9ddbb2d1913c1588a919fdb29d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/soc/amd/common/block/psp/psp_gen2.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 92063d6cdb..e4adc8bf39 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -3,6 +3,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <timer.h>
+#include <types.h>
 #include <amdblocks/psp.h>
 #include <amdblocks/smn.h>
 #include "psp_def.h"
@@ -12,7 +13,10 @@
 #define PSP_MAILBOX_BUFFER_H_OFFSET	0x10578 /* 4 bytes */
 
 #define CORE_2_PSP_MSG_38_OFFSET	0x10998 /* 4 byte */
-#define   CORE_2_PSP_MSG_38_FUSE_SPL	BIT(12)
+#define   CORE_2_PSP_MSG_38_FUSE_SPL		BIT(12)
+#define   CORE_2_PSP_MSG_38_SPL_FUSE_ERROR	BIT(13)
+#define   CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR	BIT(14)
+#define   CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING	BIT(15)
 
 union pspv2_mbox_command {
 	u32 val;
@@ -131,6 +135,22 @@ void psp_set_spl_fuse(void *unused)
 		return;
 	}
 
+	if (c2p38 & CORE_2_PSP_MSG_38_SPL_FUSE_ERROR) {
+		printk(BIOS_ERR, "PSP: SPL Table does not meet fuse requirements.\n");
+		return;
+	}
+
+	if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR) {
+		printk(BIOS_ERR, "PSP: Critical SPL entry missing or current firmware does"
+				   " not meet requirements.\n");
+		return;
+	}
+
+	if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING) {
+		printk(BIOS_ERR, "PSP: Table of critical SPL values is missing.\n");
+		return;
+	}
+
 	if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL))
 		return;