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nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__ 

Change-Id: I93351a2716cd58c2006400cecca1390b1704e94b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4603
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Vladimir Serbinenko 2014-01-02 10:10:14 +01:00
parent 517406aac7
commit bd89699516
1 changed files with 4 additions and 5 deletions
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9
src/northbridge/intel/nehalem/acpi.c
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@ -21,6 +21,8 @@
* MA 02110-1301 USA * MA 02110-1301 USA
*/ */
#define __SIMPLE_DEVICE__
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <console/console.h> #include <console/console.h>
@ -38,10 +40,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar_reg; u32 pciexbar_reg;
int max_buses; int max_buses;
/* Quickpath bus is not in standard coreboot device tree, pciexbar_reg = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x50);
so read register directly. */
pciexbar_reg = read32(DEFAULT_PCIEXBAR
| (QUICKPATH_BUS << 20) | 0x1050);
// MMCFG not supported or not enabled. // MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0))) if (!(pciexbar_reg & (1 << 0)))
@ -173,7 +172,7 @@ int init_igd_opregion(igd_opregion_t * opregion)
/* TODO This needs to happen in S3 resume, too. /* TODO This needs to happen in S3 resume, too.
* Maybe it should move to the finalize handler * Maybe it should move to the finalize handler
*/ */
igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); igd = PCI_DEV(0, 0x2, 0);
pci_write_config32(igd, ASLS, (u32) opregion); pci_write_config32(igd, ASLS, (u32) opregion);
reg16 = pci_read_config16(igd, SWSCI); reg16 = pci_read_config16(igd, SWSCI);