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soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry 

This is a W/A to avoid a communication issue with CSE Lite over Heci
interface. This will help to avoid boot failures with CSE Lite until
the permanent fix is available.

BUG=b:159884143
TEST=build and boot volteer with serial and non-serial image

Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jamie Ryu 2020-06-24 18:29:06 -07:00 committed by Tim Wawrzynczak
parent bc76cf56a4
commit bd8e761be2
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/common/block/cse/cse_lite.c
View File

@ -361,4 +361,8 @@ void cse_fw_sync(void *unused)
}
}
#if CONFIG(SOC_INTEL_TIGERLAKE)
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL);
#else
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
#endif