mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVP
This patch adds initial bootblock code. This also configures required GPIOs for early board initialization. 1. Add bootblock file for MTL-RVP 2. Add early gpio config for MTL-P variant in gpio.c BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform to ChromeOS with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -2,6 +2,8 @@
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all-$(CONFIG_CHROMEOS) += chromeos.c
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all-$(CONFIG_CHROMEOS) += chromeos.c
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bootblock-y += bootblock.c
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ramstage-y += ec.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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ramstage-y += mainboard.c
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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void bootblock_mainboard_early_init(void)
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{
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configure_early_gpio_pads();
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}
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@ -12,4 +12,7 @@ enum mtl_boardid {
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MTLM_LP5_RVP = 0x06,
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MTLM_LP5_RVP = 0x06,
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};
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};
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/* Functions to configure GPIO as per variant schematics */
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void configure_early_gpio_pads(void);
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#endif /*__BASEBOARD_VARIANTS_H__ */
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#endif /*__BASEBOARD_VARIANTS_H__ */
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@ -1,3 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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## SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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@ -1,8 +1,67 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <ec/intel/board_id.h>
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#include <soc/soc_info.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Early pad configuration in bootblock */
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static const struct pad_config mtl_p_rvp_early_gpio_table[] = {
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/* Audio */
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PAD_NC(GPP_D14, NONE), /* M.2_BT_I2S2_PCMCLK/NONE */
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PAD_NC(GPP_D15, NONE), /* M.2_BT_I2S2_PCMFRM/NONE */
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PAD_CFG_GPO(GPP_S04, 1, DEEP), /* EN_SPKR_PA */
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PAD_CFG_GPI_INT(GPP_S05, NONE, PLTRST, EDGE_BOTH),
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/* SMBUS */
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PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* GPP_C0_SMBCLK */
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PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* GPP_C1_SMBDATA */
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/* SSD */
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PAD_CFG_GPO(GPP_B15, 0, DEEP), /* M.2_CPU_SSD3_PWREN */
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PAD_CFG_GPO(GPP_D06, 0, DEEP), /* M.2_CPU_SSD4_PWREN */
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};
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static const struct pad_config early_uart_gpio_table[] = {
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/* UART0 */
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PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */
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PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */
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};
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static const struct pad_config early_wwan_on_gpio_table[] = {
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/* M.2 WWAN */
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PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PWREN */
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PAD_CFG_GPO(GPP_E07, 1, DEEP), /* M.2_WWAN_FCP_OFF_N */
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PAD_CFG_GPO(GPP_A15, 0, DEEP), /* M.2_WWAN_RST_N */
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PAD_CFG_GPO(GPP_C05, 0, DEEP), /* M.2_WWAN_PERST_GPIO_N */
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PAD_CFG_GPI_SCI(GPP_F10, NONE, DEEP, LEVEL, INVERT), /* M.2_WWAN_WAKE_GPIO_N */
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};
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void configure_early_gpio_pads(void)
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{
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uint8_t board_id = get_rvp_board_id();
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if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
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gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
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switch (board_id) {
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case MTLP_DDR5_RVP:
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case MTLP_LP5_T3_RVP:
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case MTLP_LP5_T4_RVP:
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gpio_configure_pads(mtl_p_rvp_early_gpio_table,
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ARRAY_SIZE(mtl_p_rvp_early_gpio_table));
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gpio_configure_pads(early_wwan_on_gpio_table,
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ARRAY_SIZE(early_wwan_on_gpio_table));
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break;
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default:
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printk(BIOS_WARNING, "Invalid board_id 0x%x."
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"Skipping early gpio configuration\n", board_id);
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break;
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}
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}
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static const struct cros_gpio cros_gpios[] = {
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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};
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};
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