From bd9b044a96cc3686163490744466c9b44d81846e Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Thu, 23 Sep 2021 07:48:19 -0600 Subject: [PATCH] mb/system76: rtd3: Remove SrcClk pin on CPU RP Setting srcclk_pin only works for PCH PCIe devices. Disable them on the CPU RP and add a TODO. Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4 Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller --- src/mainboard/system76/darp7/devicetree.cb | 3 ++- src/mainboard/system76/galp5/devicetree.cb | 3 ++- src/mainboard/system76/lemp10/devicetree.cb | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index c357ed1ac8..43bbdb8ff4 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -117,7 +117,8 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST# - register "srcclk_pin" = "0" # SSD1_CLKREQ# + # TODO: Support disable/enable CPU RP clock + register "srcclk_pin" = "-1" # SSD1_CLKREQ# device generic 0 on end end end diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index e6b7e4de1e..12f67df9d3 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -117,7 +117,8 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 - register "srcclk_pin" = "0" # SSD1_CLKREQ# + # TODO: Support disable/enable CPU RP clock + register "srcclk_pin" = "-1" # SSD1_CLKREQ# device generic 0 on end end end diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index eabb25c774..45d4016818 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -118,7 +118,8 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly) - register "srcclk_pin" = "3" + # TODO: Support disable/enable CPU RP clock + register "srcclk_pin" = "-1" # SSD2_CLKREQ# device generic 0 on end end end