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mb/google/brya/var/vell: Remove unused i2c7 settings 

This patch removes unused i2c7 settings. Accroding to EVT schematic,
i2c7 is reserved for AMP but resistors are unstuffing.

BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
     && checks EC log and ensures the DUT could enter s0ix.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Gaggery Tsai 2022-04-27 08:39:30 -07:00 committed by Felix Held
parent 405c73005f
commit bd9cec8ae5
2 changed files with 5 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/brya/variants/vell/gpio.c
View File

@ -57,10 +57,10 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
/* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
/* H12 : I2C7_SDA ==> UWB_SDA */ /* H12 : Reserved I2C7_SDAL for AMP */
PAD_CFG_NF_LOCK(GPP_H12, NONE, NF1, LOCK_CONFIG), PAD_NC(GPP_H12, NONE),
/* H13 : I2C7_SCL ==> UWB_SCL */ /* H13 : Reserved I2C7_SCL for AMP */
PAD_CFG_NF_LOCK(GPP_H13, NONE, NF1, LOCK_CONFIG), PAD_NC(GPP_H13, NONE),
/* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */ /* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6), PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6),
/* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */ /* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */

12
src/mainboard/google/brya/variants/vell/overridetree.cb
View File

@ -57,15 +57,6 @@ chip soc/intel/alderlake
.fall_time_ns = 400, .fall_time_ns = 400,
.data_hold_time_ns = 50, .data_hold_time_ns = 50,
}, },
.i2c[7] = {
.speed = I2C_SPEED_FAST_PLUS,
.speed_config[0] = {
.speed = I2C_SPEED_FAST_PLUS,
.scl_lcnt = 45,
.scl_hcnt = 30,
.sda_hold = 20,
},
},
}" }"
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
@ -83,7 +74,7 @@ chip soc/intel/alderlake
[PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C7] = PchSerialIoPci, [PchSerialIoIndexI2C7] = PchSerialIoDisabled,
}" }"
device domain 0 on device domain 0 on
device ref igpu on device ref igpu on
@ -358,7 +349,6 @@ chip soc/intel/alderlake
device i2c 15 on end device i2c 15 on end
end end
end end
device ref i2c7 on end
device ref gspi1 on device ref gspi1 on
chip drivers/spi/acpi chip drivers/spi/acpi
register "name" = ""CRFP"" register "name" = ""CRFP""