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soc/intel/cannonlake: Align cosmetics with Ice Lake 

By ironing out cosmetic differences between Cannon Lake and Ice Lake,
comparing actual code differences using a diff tool becomes simpler.

Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.

Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Angel Pons 2020-09-28 01:10:40 +02:00 committed by Nico Huber
parent 8c8b34996d
commit bda02b0f2b
4 changed files with 46 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/cannonlake/acpi/pch_hda.asl
View File

@ -4,7 +4,7 @@
Device (HDAS)
{
Name (_ADR, 0x001F0003)
Name (_ADR, 0x001f0003)
Name (_DDN, "Audio Controller")
Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))

57
src/soc/intel/cannonlake/cpu.c
View File

@ -54,9 +54,10 @@ static void configure_isst(void)
static void configure_misc(void)
{
config_t *conf = config_of_soc();
msr_t msr;
config_t *conf = config_of_soc();
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
@ -105,6 +106,33 @@ static void configure_dca_cap(void)
}
}
/*
* The emulated ACPI timer allows replacing of the ACPI timer
* (PM1_TMR) to have no impart on the system.
*/
static void enable_pm_timer_emulation(void)
{
const struct soc_intel_cannonlake_config *config;
msr_t msr;
config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */
if (!config->PmTimerDisabled)
return;
/*
* The derived frequency is calculated as follows:
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
* Back solve the multiplier so the 3.579545MHz ACPI timer
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
static void set_energy_perf_bias(u8 policy)
{
msr_t msr;
@ -155,33 +183,6 @@ static void configure_c_states(void)
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
/*
* The emulated ACPI timer allows replacing of the ACPI timer
* (PM1_TMR) to have no impart on the system.
*/
static void enable_pm_timer_emulation(void)
{
const struct soc_intel_cannonlake_config *config;
msr_t msr;
config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */
if (!config->PmTimerDisabled)
return;
/*
* The derived frequency is calculated as follows:
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
* Back solve the multiplier so the 3.579545MHz ACPI timer
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{

35
src/soc/intel/cannonlake/me.c
View File

@ -12,7 +12,7 @@
/* Host Firmware Status Register 2 */
union me_hfsts2 {
uint32_t raw;
uint32_t data;
struct {
uint32_t nftp_load_failure : 1;
uint32_t icc_prog_status : 2;
@ -36,7 +36,7 @@ union me_hfsts2 {
/* Host Firmware Status Register 4 */
union me_hfsts4 {
uint32_t raw;
uint32_t data;
struct {
uint32_t rsvd0 : 9;
uint32_t enforcement_flow : 1;
@ -52,7 +52,7 @@ union me_hfsts4 {
/* Host Firmware Status Register 5 */
union me_hfsts5 {
uint32_t raw;
uint32_t data;
struct {
uint32_t acm_active : 1;
uint32_t valid : 1;
@ -71,7 +71,7 @@ union me_hfsts5 {
/* Host Firmware Status Register 6 */
union me_hfsts6 {
uint32_t raw;
uint32_t data;
struct {
uint32_t force_boot_guard_acm : 1;
uint32_t cpu_debug_disable : 1;
@ -107,24 +107,18 @@ void dump_me_status(void *unused)
return;
hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
hfsts2.raw = me_read_config32(PCI_ME_HFSTS2);
hfsts2.data = me_read_config32(PCI_ME_HFSTS2);
hfsts3.data = me_read_config32(PCI_ME_HFSTS3);
hfsts4.raw = me_read_config32(PCI_ME_HFSTS4);
hfsts5.raw = me_read_config32(PCI_ME_HFSTS5);
hfsts6.raw = me_read_config32(PCI_ME_HFSTS6);
hfsts4.data = me_read_config32(PCI_ME_HFSTS4);
hfsts5.data = me_read_config32(PCI_ME_HFSTS5);
hfsts6.data = me_read_config32(PCI_ME_HFSTS6);
printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n",
hfsts1.data);
printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n",
hfsts2.raw);
printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n",
hfsts3.data);
printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n",
hfsts4.raw);
printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n",
hfsts5.raw);
printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n",
hfsts6.raw);
printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data);
printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data);
printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data);
printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data);
printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data);
printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data);
printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n",
hfsts1.fields.mfg_mode ? "YES" : "NO");
@ -159,5 +153,6 @@ void dump_me_status(void *unused)
printk(BIOS_DEBUG, "ME: TXT Support : %s\n",
hfsts6.fields.txt_support ? "YES" : "NO");
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL);
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL);

2
src/soc/intel/cannonlake/sd.c
View File

@ -3,7 +3,7 @@
#include <intelblocks/sd.h>
#include "chip.h"
int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev)
int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev)
{
config_t *config = config_of(dev);