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For AMD family 10h processors, msr c0010058 is always programmed 

for 256 buses, even if fewer are configured. This patch lets msr
c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2010-10-19 21:08:11 +00:00
parent 115e66018a
commit bda153be73
1 changed files with 28 additions and 8 deletions
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36
src/cpu/amd/car/cache_as_ram.inc
View File

@ -132,14 +132,34 @@ CAR_FAM10_out:
wrmsr wrmsr
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
/* Set MMIO config space BAR. */ #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
movl $MSR_MCFG_BASE, %ecx #error "MMCONF_BASE_ADDRESS too big"
rdmsr #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
andl $(~(0xfff00000 | (0xf << 2))), %eax #error "MMCONF_BASE_ADDRESS not 1MB aligned"
orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000)), %eax #endif
orl $((8 << 2) | (1 << 0)), %eax movl $0, %edx
andl $(~(0x0000ffff)), %edx movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx #if (CONFIG_MMCONF_BUS_NUMBER == 1)
#elif (CONFIG_MMCONF_BUS_NUMBER == 2)
orl $(1 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 4)
orl $(2 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 8)
orl $(3 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 16)
orl $(4 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 32)
orl $(5 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 64)
orl $(6 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 128)
orl $(7 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 256)
orl $(8 << 2), %eax
#else
#error "bad MMCONF_BUS_NUMBER value"
#endif
movl $(0xc0010058), %ecx
wrmsr wrmsr
#endif #endif