src: Remove whitespaces before tabs

Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex

@@ -170,7 +170,7 @@ F0
 00
 
 #	33 SDRAM device type
-# 		byte [1:0] : 00b = Signal Loading not specified
+#		byte [1:0] : 00b = Signal Loading not specified
 #		byte [6:4] : 000b = Die count not specified
 #		byte [7]   : 0 = Standard Monolithic DRAM Device
 00

src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex

@@ -170,7 +170,7 @@ F0
 00
 
 #	33 SDRAM device type
-# 		byte [1:0] : 00b = Signal Loading not specified
+#		byte [1:0] : 00b = Signal Loading not specified
 #		byte [6:4] : 000b = Die count not specified
 #		byte [7]   : 1 = Non-Standard Device
 80

src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex

@@ -168,7 +168,7 @@ FE
 
 #	33 SDRAM device type
 #		byte [1:0] : 01b = multi load stack
-# 		byte [6:4] : 100b = 8 die
+#		byte [6:4] : 100b = 8 die
 #		byte [7]   : 0 = Standard Device
 41
 

src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex

@@ -170,7 +170,7 @@ F0
 00
 
 #	33 SDRAM device type
-# 		byte [1:0] : 00b = Signal Loading not specified
+#		byte [1:0] : 00b = Signal Loading not specified
 #		byte [6:4] : 000b = Die count not specified
 #		byte [7]   : 0 = Standard Monolithic DRAM Device
 00

src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex

@@ -170,7 +170,7 @@ F0
 00
 
 #	33 SDRAM device type
-# 		byte [1:0] : 00b = Signal Loading not specified
+#		byte [1:0] : 00b = Signal Loading not specified
 #		byte [6:4] : 000b = Die count not specified
 #		byte [7]   : 1 = Non-Standard Device
 80

src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex

@@ -168,7 +168,7 @@ FE
 
 #	33 SDRAM device type
 #		byte [1:0] : 01b = multi load stack
-# 		byte [6:4] : 100b = 8 die
+#		byte [6:4] : 100b = 8 die
 #		byte [7]   : 0 = Standard Device
 41
 

src/mainboard/prodrive/hermes/devicetree.cb

@@ -34,7 +34,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end  # Aspeed 2500 VGA
 			end
 		end # PCIe
-		device pci 1f.0 on 	# LPC Interface
+		device pci 1f.0 on	# LPC Interface
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
 			end

src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb

@@ -25,7 +25,7 @@ chip soc/intel/cannonlake
 	# Enumeration starts at 0 for PCIE1
 	# Ports are not hotplugable
 	register "PcieRpEnable[0]" = "1"	# Slot3 x4
- 	# Set MaxPayload to 256 bytes
+	# Set MaxPayload to 256 bytes
 	register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
 	# Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[0]" = "1"

src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb

@@ -93,7 +93,7 @@ chip soc/intel/apollolake
 		device pci 1c.0 on  end	# - eMMC
 		device pci 1d.0 off end	# - UFS
 		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on  	# - LPC
+		device pci 1f.0 on	# - LPC
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
 			end

src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb

@@ -108,7 +108,7 @@ chip soc/intel/apollolake
 		device pci 1c.0 on  end	# - eMMC
 		device pci 1d.0 off end	# - UFS
 		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on  	# - LPC
+		device pci 1f.0 on	# - LPC
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
 			end

src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb

@@ -72,7 +72,7 @@ chip soc/intel/apollolake
 		device pci 1c.0 off end	# - eMMC
 		device pci 1d.0 off end	# - UFS
 		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on  	# - LPC
+		device pci 1f.0 on	# - LPC
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
 			end

src/soc/intel/cannonlake/acpi/scs.asl

@@ -82,7 +82,7 @@ Scope (\_SB.PCI0) {
 					 * containing one bit for each function index, starting
 					 * with zero.
 					 * Bit 0 - Indicates whether there is support for any
-					 * 	   functions other than function 0
+					 *	   functions other than function 0
 					 * Bit 1 - Indicates support to clear power control
 					 *	   register
 					 * Bit 2 - Indicates support to set power control

src/soc/intel/common/acpi/lpit.asl

@@ -69,7 +69,7 @@ Scope(\_SB)
 				/*
 				 * Save the current PM bits then
 				 * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
- 				 */
+				 */
 				If (CondRefOf (\_SB.PCI0.EGPM))
 				{
 					\_SB.PCI0.EGPM ()

src/soc/intel/tigerlake/acpi/tcss_dma.asl

@@ -56,7 +56,7 @@ Method (_PR3)
  */
 Method (D3CX, 0, Serialized)
 {
-	DD3E = 0  	/* Disable DMA RTD3 */
+	DD3E = 0	/* Disable DMA RTD3 */
 	STAT = 0x1
 }
 
@@ -65,7 +65,7 @@ Method (D3CX, 0, Serialized)
  */
 Method (D3CE, 0, Serialized)
 {
-	DD3E = 1  	/* Enable DMA RTD3 */
+	DD3E = 1	/* Enable DMA RTD3 */
 	STAT = 0
 }
 

src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl

@@ -6,7 +6,7 @@
  * The mapping fields ae Address, Pin, Source, Source Index.
  */
 
-#define GEN_PCIE_LEGACY_IRQ() 					\
+#define GEN_PCIE_LEGACY_IRQ()					\
 	Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },	\
 	Package () { 0x0001FFFF, 0x01, LNKB, 0x00 },	\
 	Package () { 0x0002FFFF, 0x02, LNKC, 0x00 },	\