arm64: add psci support to secmon
The PSCI functionality initially includes CPU_ON and CPU_OFF
functions. Upon entering secmon if the parameters are non-NULL
then a PSCI CPU_ON action is done for the current CPU.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Booted kernel with PSCI support. Brought up all CPUs in kernel
using PSCI. Turned CPUs on and off.
Change-Id: I256fa45a1c9889ff9d7990eb1898df1ec241c117
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 689ba03e313e7e52e9b74aa774897b55cbd52748
Original-Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9097
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Aaron Durbin
Patrick Georgi
parent
93eea8822d
commit
bda3577d0c
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@ -32,6 +32,7 @@ secmon-c-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kc
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secmon-S-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__
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secmon-y += secmon_init.c
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secmon-y += psci.c
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secmon-y += smc.c
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secmon-y += trampoline.S
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secmon-y += ../exception.c
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@ -0,0 +1,208 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#include <string.h>
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#include <stdlib.h>
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#include <smp/spinlock.h>
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#include <arch/cpu.h>
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#include <arch/psci.h>
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#include <arch/smc.h>
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#include <arch/transition.h>
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#include <arch/lib_helpers.h>
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#include <console/console.h>
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#include "secmon.h"
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enum {
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PSCI_CPU_STATE_OFF = 0,
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PSCI_CPU_STATE_ON_PENDING,
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PSCI_CPU_STATE_ON,
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};
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struct psci_cpu_state {
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uint64_t mpidr;
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void *entry;
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void *arg;
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int state;
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};
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DECLARE_SPIN_LOCK(psci_spinlock);
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static struct psci_cpu_state psci_state[CONFIG_MAX_CPUS];
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static inline void psci_lock(void)
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{
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spin_lock(&psci_spinlock);
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}
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static inline void psci_unlock(void)
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{
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spin_unlock(&psci_spinlock);
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}
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static inline int psci_cpu_state_locked(int i)
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{
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return psci_state[i].state;
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}
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static inline void psci_cpu_set_state_locked(int i, int s)
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{
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psci_state[i].state = s;
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}
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static struct cpu_info *mpidr_to_cpu_info(uint64_t mpidr)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(psci_state); i++) {
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if (mpidr == psci_state[i].mpidr)
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return cpu_info_for_cpu(i);
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}
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return NULL;
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}
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static void psci_cpu_on_callback(void *arg)
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{
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struct psci_cpu_state *s = arg;
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psci_turn_on_self(s->entry, s->arg);
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}
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static void psci_cpu_on(struct psci_func *pf)
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{
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uint64_t entry;
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uint64_t target_mpidr;
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uint64_t context_id;
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struct cpu_info *ci;
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int cpu_state;
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struct cpu_action action;
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target_mpidr = psci64_arg(pf, PSCI_PARAM_0);
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entry = psci64_arg(pf, PSCI_PARAM_1);
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context_id = psci64_arg(pf, PSCI_PARAM_2);
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ci = mpidr_to_cpu_info(target_mpidr);
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if (ci == NULL) {
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psci32_return(pf, PSCI_RET_INVALID_PARAMETERS);
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return;
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}
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psci_lock();
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cpu_state = psci_cpu_state_locked(ci->id);
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if (cpu_state == PSCI_CPU_STATE_ON_PENDING) {
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psci32_return(pf, PSCI_RET_ON_PENDING);
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psci_unlock();
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return;
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} else if (cpu_state == PSCI_CPU_STATE_ON) {
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psci32_return(pf, PSCI_RET_ALREADY_ON);
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psci_unlock();
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return;
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}
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psci_cpu_set_state_locked(ci->id, PSCI_CPU_STATE_ON_PENDING);
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/* Set the parameters and initialize the action. */
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psci_state[ci->id].entry = (void *)(uintptr_t)entry;
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psci_state[ci->id].arg = (void *)(uintptr_t)context_id;
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action.run = &psci_cpu_on_callback;
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action.arg = &psci_state[ci->id];
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if (arch_run_on_cpu_async(ci->id, &action)) {
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psci32_return(pf, PSCI_RET_INTERNAL_FAILURE);
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psci_unlock();
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return;
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}
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psci_unlock();
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psci32_return(pf, PSCI_RET_SUCCESS);
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}
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static void psci_cpu_off(struct psci_func *pf)
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{
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psci_lock();
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psci_cpu_set_state_locked(cpu_info()->id, PSCI_CPU_STATE_OFF);
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psci_unlock();
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/* TODO(adurbin): writeback cache and actually turn off CPU. */
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secmon_trampoline(&secmon_wait_for_action, NULL);
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}
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static int psci_handler(struct smc_call *smc)
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{
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struct psci_func pf_storage;
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struct psci_func *pf = &pf_storage;
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psci_func_init(pf, smc);
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switch (pf->id) {
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case PSCI_CPU_ON64:
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psci_cpu_on(pf);
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break;
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case PSCI_CPU_OFF64:
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psci_cpu_off(pf);
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break;
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default:
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psci32_return(pf, PSCI_RET_NOT_SUPPORTED);
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break;
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}
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return 0;
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}
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void psci_init(void)
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{
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struct cpu_info *ci;
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uint64_t mpidr;
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/* Set this CPUs MPIDR clearing the bits that are not per-cpu. */
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ci = cpu_info();
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mpidr = raw_read_mpidr_el1();
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mpidr &= ~(1ULL << 31); /* RES1 */
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mpidr &= ~(1ULL << 30); /* U */
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mpidr &= ~(1ULL << 24); /* MT */
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psci_state[ci->id].mpidr = mpidr;
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if (!cpu_is_bsp())
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return;
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/* Register PSCI handlers. */
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if (smc_register_range(PSCI_CPU_OFF64, PSCI_CPU_ON64, &psci_handler))
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printk(BIOS_ERR, "Couldn't register PSCI handler.\n");
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}
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void psci_turn_on_self(void *entry, void *arg)
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{
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struct exc_state state;
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int target_el;
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struct cpu_info *ci = cpu_info();
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psci_lock();
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psci_cpu_set_state_locked(ci->id, PSCI_CPU_STATE_ON);
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psci_unlock();
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/* Target EL is determined if HVC is enabled or not. */
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target_el = (raw_read_scr_el3() & SCR_HVC_ENABLE) ? EL2 : EL1;
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memset(&state, 0, sizeof(state));
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state.elx.spsr = get_eret_el(target_el, SPSR_USE_H);
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transition_with_entry(entry, arg, &state);
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}
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@ -23,11 +23,10 @@
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#include <arch/io.h>
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#include <arch/exception.h>
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#include <arch/lib_helpers.h>
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#include <arch/psci.h>
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#include <arch/secmon.h>
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#include <arch/smc.h>
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#include <arch/transition.h>
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#include <console/console.h>
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#include <rmodule.h>
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#include <stddef.h>
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#include "secmon.h"
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@ -44,25 +43,16 @@ static void cpu_init(int bsp)
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static void secmon_init(struct secmon_params *params, int bsp)
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{
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struct exc_state exc_state;
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exception_hwinit();
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cpu_init(bsp);
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smc_init();
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psci_init();
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/*
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* Check if the arg is non-NULL
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* 1) If yes, we make an EL2 transition to that entry point
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* 2) If no, we just wait
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*/
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if (params != NULL) {
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memset(&exc_state, 0, sizeof(exc_state));
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exc_state.elx.spsr =
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get_eret_el(params->elx_el, params->elx_mode);
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/* Turn on CPU if params are not NULL. */
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if (params != NULL)
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psci_turn_on_self(params->entry, params->arg);
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transition_with_entry(params->entry, params->arg, &exc_state);
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}
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secmon_wait_for_action();
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}
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@ -0,0 +1,115 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#ifndef __ARCH_PSCI_H__
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#define __ARCH_PSCI_H__
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#include <arch/smc.h>
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/* Return Values */
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enum {
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PSCI_RET_SUCCESS = 0,
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PSCI_RET_NOT_SUPPORTED = -1,
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PSCI_RET_INVALID_PARAMETERS = -2,
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PSCI_RET_DENIED = -3,
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PSCI_RET_ALREADY_ON = -4,
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PSCI_RET_ON_PENDING = -5,
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PSCI_RET_INTERNAL_FAILURE = -6,
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PSCI_RET_NOT_PRESENT = -7,
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PSCI_RET_DISABLED = -8,
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};
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/* PSCI Functions. */
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enum {
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/* 32-bit System level functions. */
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PSCI_VERSION = SMC_FUNC_FAST32(0x4, 0x0),
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PSCI_SYSTEM_OFF = SMC_FUNC_FAST32(0x4, 0x8),
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PSCI_SYSTEM_RESET = SMC_FUNC_FAST32(0x4, 0x9),
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/* 32-bit CPU support functions. */
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PSCI_CPU_SUSPEND32 = SMC_FUNC_FAST32(0x4, 0x1),
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PSCI_CPU_OFF32 = SMC_FUNC_FAST32(0x4, 0x2),
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PSCI_CPU_ON32 = SMC_FUNC_FAST32(0x4, 0x3),
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/* 64-bit CPU support functions. */
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PSCI_CPU_SUSPEND64 = SMC_FUNC_FAST64(0x4, 0x1),
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PSCI_CPU_OFF64 = SMC_FUNC_FAST64(0x4, 0x2),
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PSCI_CPU_ON64 = SMC_FUNC_FAST64(0x4, 0x3),
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};
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/* Parameter arguments. */
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enum {
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PSCI_PARAM_0 = 1,
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PSCI_PARAM_1,
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PSCI_PARAM_2,
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PSCI_PARAM_3,
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PSCI_RETURN_0 = 1,
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PSCI_RETURN_1,
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PSCI_RETURN_2,
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PSCI_RETURN_3,
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};
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struct psci_func {
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uint32_t id;
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struct smc_call *smc;
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};
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static inline void psci_func_init(struct psci_func *pf, struct smc_call *smc)
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{
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pf->id = smc_function_id(smc);
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pf->smc = smc;
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}
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static inline uint64_t psci64_arg(struct psci_func *pf, unsigned i)
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{
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return smc64_arg(pf->smc, i);
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}
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static inline uint32_t psci32_arg(struct psci_func *pf, unsigned i)
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{
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return psci64_arg(pf, i);
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}
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static inline void psci64_result(struct psci_func *pf, unsigned i, uint64_t v)
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{
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smc64_result(pf->smc, i, v);
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}
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static inline void psci32_result(struct psci_func *pf, unsigned i, uint32_t v)
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{
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uint64_t v64 = v;
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psci64_result(pf, i, v64);
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}
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static inline void psci32_return(struct psci_func *pf, int32_t val)
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{
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psci32_result(pf, 0, val);
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}
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static inline void psci64_return(struct psci_func *pf, int64_t val)
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{
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psci64_result(pf, 0, val);
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}
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void psci_init(void);
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/* Turn on the current CPU within the PSCI subsystem. */
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void psci_turn_on_self(void *entry, void *arg);
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#endif /* __ARCH_PSCI_H__ */
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