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Use easily readable macros to setup interrupt routing. 

Change a few PCI bus/dev/fn to use hexadecimal numbers.
Kill unused variables.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger 2008-10-02 00:52:53 +00:00
parent 5263b01657
commit bdb96f8abe
1 changed files with 54 additions and 82 deletions
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136
src/mainboard/amd/dbm690t/mptable.c
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@ -45,7 +45,6 @@ void *smp_write_config_table(void *v)
static const char oem[8] = "ATI "; static const char oem[8] = "ATI ";
static const char productid[12] = "DBM690T "; static const char productid[12] = "DBM690T ";
struct mp_config_table *mc; struct mp_config_table *mc;
int i, j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
@ -119,104 +118,77 @@ void *smp_write_config_table(void *v)
} }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, #define IO_LOCAL_INT(type, intr, apicid, pin) \
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
0x0, apicid_sb600, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
bus_isa, 0x1, apicid_sb600, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, /* ISA ints are edge-triggered, and usually originate from the ISA bus,
bus_isa, 0x0, apicid_sb600, 0x2); * or its remainings.
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, */
bus_isa, 0x3, apicid_sb600, 0x3); #define ISA_INT(intr, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin))
bus_isa, 0x4, apicid_sb600, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, ISA_INT(0x1, 0x1);
bus_isa, 0x6, apicid_sb600, 0x6); ISA_INT(0x0, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, ISA_INT(0x3, 0x3);
bus_isa, 0x7, apicid_sb600, 0x7); ISA_INT(0x4, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, ISA_INT(0x6, 0x6);
bus_isa, 0xc, apicid_sb600, 0xc); ISA_INT(0x7, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, ISA_INT(0xc, 0xc);
bus_isa, 0xd, apicid_sb600, 0xd); ISA_INT(0xd, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, ISA_INT(0xe, 0xe);
bus_isa, 0xe, apicid_sb600, 0xe);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
/* usb */ /* usb */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(0x0, 0x13, 0x0, 0x10);
0, 19 << 2 | 0, apicid_sb600, 0x10); PCI_INT(0x0, 0x13, 0x1, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(0x0, 0x13, 0x2, 0x12);
0, 19 << 2 | 1, apicid_sb600, 0x11); PCI_INT(0x0, 0x13, 0x3, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
0, 19 << 2 | 2, apicid_sb600, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
0, 19 << 2 | 3, apicid_sb600, 0x13);
/* sata */ /* sata */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(0x0, 0x12, 0x0, 0x16);
0, 18 << 2 | 0, apicid_sb600, 22);
/* HD Audio: b0:d20:f1:reg63 should be 0. */ /* HD Audio: b0:d20:f1:reg63 should be 0. */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(0x0, 0x14, 0x0, 0x10);
0, 20 << 2 | 0, apicid_sb600, 16);
/* on board NIC & Slot PCIE. */ /* on board NIC & Slot PCIE. */
i = 2; PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18); PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19); PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18); PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19);
/* PCI slots */ /* PCI slots */
i += 6;
j = 5;
/* PCI_SLOT 0. */ /* PCI_SLOT 0. */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20); PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21); PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23);
/* PCI_SLOT 1. */ /* PCI_SLOT 1. */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21); PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22); PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20);
/* PCI_SLOT 2. */ /* PCI_SLOT 2. */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22); PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */ /* There is no extension information... */
/* Compute the checksums */ /* Compute the checksums */