Use easily readable macros to setup interrupt routing.
Change a few PCI bus/dev/fn to use hexadecimal numbers. Kill unused variables. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -45,7 +45,6 @@ void *smp_write_config_table(void *v)
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static const char oem[8] = "ATI ";
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static const char productid[12] = "DBM690T ";
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struct mp_config_table *mc;
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int i, j;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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@ -119,104 +118,77 @@ void *smp_write_config_table(void *v)
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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smp_write_intsrc(mc, mp_ExtINT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
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0x0, apicid_sb600, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x1, apicid_sb600, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x0, apicid_sb600, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x3, apicid_sb600, 0x3);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x4, apicid_sb600, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x6, apicid_sb600, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x7, apicid_sb600, 0x7);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0xc, apicid_sb600, 0xc);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0xd, apicid_sb600, 0xd);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0xe, apicid_sb600, 0xe);
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
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/* ISA ints are edge-triggered, and usually originate from the ISA bus,
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* or its remainings.
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*/
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#define ISA_INT(intr, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin))
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ISA_INT(0x1, 0x1);
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ISA_INT(0x0, 0x2);
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ISA_INT(0x3, 0x3);
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ISA_INT(0x4, 0x4);
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ISA_INT(0x6, 0x6);
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ISA_INT(0x7, 0x7);
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ISA_INT(0xc, 0xc);
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ISA_INT(0xd, 0xd);
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ISA_INT(0xe, 0xe);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
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/* usb */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0, 19 << 2 | 0, apicid_sb600, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0, 19 << 2 | 1, apicid_sb600, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0, 19 << 2 | 2, apicid_sb600, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0, 19 << 2 | 3, apicid_sb600, 0x13);
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PCI_INT(0x0, 0x13, 0x0, 0x10);
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PCI_INT(0x0, 0x13, 0x1, 0x11);
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PCI_INT(0x0, 0x13, 0x2, 0x12);
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PCI_INT(0x0, 0x13, 0x3, 0x13);
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/* sata */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0, 18 << 2 | 0, apicid_sb600, 22);
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PCI_INT(0x0, 0x12, 0x0, 0x16);
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/* HD Audio: b0:d20:f1:reg63 should be 0. */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0, 20 << 2 | 0, apicid_sb600, 16);
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* on board NIC & Slot PCIE. */
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i = 2;
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19);
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PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
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PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
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PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
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PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
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PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
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PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
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PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
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PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
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/* PCI slots */
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i += 6;
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j = 5;
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/* PCI_SLOT 0. */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23);
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PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
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PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
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PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
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PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
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/* PCI_SLOT 1. */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20);
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PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
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PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
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PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
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PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
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/* PCI_SLOT 2. */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21);
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PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
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PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
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PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
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PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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smp_write_intsrc(mc, mp_ExtINT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
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0x0, MP_APIC_ALL, 0x0);
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smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x0, MP_APIC_ALL, 0x1);
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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