GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI 

This introduces a Kconfig option to include common Intel SPI code.

Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans 2017-09-25 12:21:07 +02:00
parent bf8db8d45b
commit bddef0dae7
14 changed files with 15 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -26,6 +26,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG_OPTIONS
@ -33,7 +34,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select COMMON_FADT
select ACPI_SATA_GENERATOR
select HAVE_INTEL_FIRMWARE

2
src/southbridge/intel/bd82x6x/Makefile.inc
View File

@ -35,8 +35,6 @@ ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += ../common/spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c

4
src/southbridge/intel/common/Kconfig
View File

@ -8,6 +8,10 @@ config SOUTHBRIDGE_INTEL_COMMON_SMBUS
def_bool n
select HAVE_DEBUG_SMBUS
config SOUTHBRIDGE_INTEL_COMMON_SPI
def_bool n
select SPI_FLASH
config HAVE_INTEL_CHIPSET_LOCKDOWN
def_bool n

5
src/southbridge/intel/common/Makefile.inc
View File

@ -28,4 +28,9 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
ifeq ($(CONFIG_SPI_FLASH_SMM),y)
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
endif
endif

2
src/southbridge/intel/fsp_bd82x6x/Kconfig
View File

@ -28,11 +28,11 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select COMMON_FADT
select HAVE_INTEL_FIRMWARE
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select HAVE_INTEL_CHIPSET_LOCKDOWN
config EHCI_BAR

2
src/southbridge/intel/fsp_bd82x6x/Makefile.inc
View File

@ -27,8 +27,6 @@ ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += ../common/spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c

2
src/southbridge/intel/fsp_i89xx/Kconfig
View File

@ -28,12 +28,12 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select COMMON_FADT
select HAVE_INTEL_FIRMWARE
select NO_EARLY_BOOTBLOCK_POSTCODES
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
config EHCI_BAR
hex

2
src/southbridge/intel/fsp_i89xx/Makefile.inc
View File

@ -26,8 +26,6 @@ ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += ../common/spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c

2
src/southbridge/intel/i82801gx/Kconfig
View File

@ -23,9 +23,9 @@ config SOUTHBRIDGE_INTEL_I82801GX
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select COMMON_FADT
select SPI_FLASH
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
if SOUTHBRIDGE_INTEL_I82801GX

1
src/southbridge/intel/i82801gx/Makefile.inc
View File

@ -27,7 +27,6 @@ ramstage-y += sata.c
ramstage-y += smbus.c
ramstage-y += usb.c
ramstage-y += usb_ehci.c
ramstage-y += ../common/spi.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c

2
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -28,9 +28,9 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select HAVE_USBDEBUG_OPTIONS
select COMMON_FADT
select ACPI_SATA_GENERATOR

2
src/southbridge/intel/ibexpeak/Makefile.inc
View File

@ -35,9 +35,7 @@ ramstage-y += ../bd82x6x/reset.c
ramstage-y += ../bd82x6x/watchdog.c
ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
ramstage-y += ../common/spi.c
ramstage-y += madt.c
smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-y += smi.c
smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c

2
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -23,13 +23,13 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
select RTC

2
src/southbridge/intel/lynxpoint/Makefile.inc
View File

@ -41,8 +41,6 @@ ramstage-y += watchdog.c
ramstage-y += acpi.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += ../common/spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c