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vexpress: change to write32 

Change-Id: I5fcc83328441ccfb34ee63a7406d26e393633c21
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/19685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Vladimir Serbinenko 2017-05-13 20:21:37 +00:00
parent 7ad44eed08
commit bddf86a259
1 changed files with 8 additions and 7 deletions
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15
src/mainboard/emulation/qemu-armv7/mainboard.c
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@ -21,25 +21,26 @@
#include <halt.h> #include <halt.h>
#include "mainboard.h" #include "mainboard.h"
#include <edid.h> #include <edid.h>
#include <arch/io.h>
static void init_gfx(void) static void init_gfx(void)
{ {
volatile uint32_t *pl111; uint32_t *pl111;
struct edid edid; struct edid edid;
/* width is at most 4096 */ /* width is at most 4096 */
/* height is at most 1024 */ /* height is at most 1024 */
int width = 800, height = 600; int width = 800, height = 600;
uint32_t framebuffer = 0x4c000000; uint32_t framebuffer = 0x4c000000;
pl111 = (uint32_t *) 0x10020000; pl111 = (uint32_t *) 0x10020000;
pl111[0] = (width / 4) - 4; write32(pl111, (width / 4) - 4);
pl111[1] = height - 1; write32(pl111 + 1, height - 1);
/* registers 2, 3 and 5 are ignored by qemu. Set them correctly if /* registers 2, 3 and 5 are ignored by qemu. Set them correctly if
we ever go for real hw. */ we ever go for real hw. */
/* framebuffer adress offset. Has to be in vram. */ /* framebuffer adress offset. Has to be in vram. */
pl111[4] = framebuffer; write32(pl111 + 4, framebuffer);
pl111[7] = 0; write32(pl111 + 7, 0);
pl111[10] = 0xff; write32(pl111 + 10, 0xff);
pl111[6] = (5 << 1) | 0x801; write32(pl111 + 6, (5 << 1) | 0x801);
edid.framebuffer_bits_per_pixel = 32; edid.framebuffer_bits_per_pixel = 32;
edid.bytes_per_line = width * 4; edid.bytes_per_line = width * 4;