mb/google/hatch/scout: Update DPTF parameters
update the DPTF parameters received from the thermal team. BUG=b:195602767 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I5dc89d1d4c2b64c9aac780a7db743a91fd0ebc9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeff Chase <jnchase@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -240,20 +240,22 @@ chip soc/intel/cannonlake
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register "policies.active[0]" = "{.target=DPTF_CPU,
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.thresholds={TEMP_PCT(94, 0),}}"
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register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
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.thresholds={TEMP_PCT(72, 90),
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TEMP_PCT(68, 80),
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TEMP_PCT(62, 70),
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TEMP_PCT(54, 60),
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TEMP_PCT(46, 50),
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TEMP_PCT(39, 40),}}"
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.thresholds={TEMP_PCT(84, 90),
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TEMP_PCT(82, 80),
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TEMP_PCT(80, 70),
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TEMP_PCT(66, 60),
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TEMP_PCT(52, 50),
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TEMP_PCT(35, 40),}}"
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## Passive Policy
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register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
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register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)"
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register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000)"
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register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000)"
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## Critical Policy
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register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
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register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
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register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)"
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register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN)"
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## Power Limits Control
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# PL1 is fixed at 15W, avg over 28-32s interval
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