x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
This commit is contained in:
Kevin Paul Herbert
Alexandru Gagniuc
parent
4b10dec1a6
commit
bde6d309df
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@ -222,7 +222,7 @@ static void smp_write_bus(struct mp_config_table *mc,
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* APIC Flags:EN, Address
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*/
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void smp_write_ioapic(struct mp_config_table *mc,
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u8 id, u8 ver, u32 apicaddr)
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u8 id, u8 ver, void *apicaddr)
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{
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struct mpc_config_ioapic *mpc;
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mpc = smp_next_mpc_entry(mc);
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@ -23,9 +23,9 @@
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#define __ARCH_EBDA_H
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#define X86_BDA_SIZE 0x200
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#define X86_BDA_BASE 0x400
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#define X86_EBDA_SEGMENT 0x40e
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#define X86_EBDA_LOWMEM 0x413
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#define X86_BDA_BASE (void *)0x400
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#define X86_EBDA_SEGMENT (void *)0x40e
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#define X86_EBDA_LOWMEM (void *)0x413
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#define DEFAULT_EBDA_LOWMEM (1024 << 10)
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#define DEFAULT_EBDA_SEGMENT 0xF600
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@ -142,32 +142,32 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
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);
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}
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static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
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static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
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{
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return *((volatile uint8_t *)(addr));
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}
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static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
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static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
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{
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return *((volatile uint16_t *)(addr));
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}
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static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
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static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
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{
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return *((volatile uint32_t *)(addr));
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}
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static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
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static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
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{
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*((volatile uint8_t *)(addr)) = value;
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}
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static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
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static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
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{
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*((volatile uint16_t *)(addr)) = value;
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}
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static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
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static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
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{
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*((volatile uint32_t *)(addr)) = value;
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}
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@ -21,6 +21,7 @@
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#define __I386_ARCH_IOAPIC_H
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#define IO_APIC_ADDR 0xfec00000
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#define VIO_APIC_VADDR ((u8 *)IO_APIC_ADDR)
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#define IO_APIC_INTERRUPTS 24
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#ifndef __ACPI__
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@ -42,11 +43,11 @@
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#define SMI (2 << 8)
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#define INT (1 << 8)
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u32 io_apic_read(u32 ioapic_base, u32 reg);
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void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
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void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
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void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
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void clear_ioapic(u32 ioapic_base);
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u32 io_apic_read(void *ioapic_base, u32 reg);
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void io_apic_write(void *ioapic_base, u32 reg, u32 value);
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void set_ioapic_id(void *ioapic_base, u8 ioapic_id);
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void setup_ioapic(void *ioapic_base, u8 ioapic_id);
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void clear_ioapic(void *ioapic_base);
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#endif
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#endif
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@ -28,48 +28,48 @@
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static inline __attribute__ ((always_inline))
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u8 pcie_read_config8(pci_devfn_t dev, unsigned int where)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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void *addr;
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addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
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return read8(addr);
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}
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static inline __attribute__ ((always_inline))
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u16 pcie_read_config16(pci_devfn_t dev, unsigned int where)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
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void *addr;
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addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
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return read16(addr);
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}
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static inline __attribute__ ((always_inline))
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u32 pcie_read_config32(pci_devfn_t dev, unsigned int where)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
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void *addr;
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addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
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return read32(addr);
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}
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static inline __attribute__ ((always_inline))
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void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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void *addr;
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addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
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write8(addr, value);
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}
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static inline __attribute__ ((always_inline))
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void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
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void *addr;
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addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
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write16(addr, value);
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}
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static inline __attribute__ ((always_inline))
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void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
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void *addr;
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addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
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write32(addr, value);
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}
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@ -123,7 +123,7 @@ struct mpc_config_ioapic
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u8 mpc_apicver;
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u8 mpc_flags;
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#define MPC_APIC_USABLE 0x01
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u32 mpc_apicaddr;
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void *mpc_apicaddr;
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} __attribute__((packed));
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struct mpc_config_intsrc
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@ -260,7 +260,7 @@ void smp_write_processor(struct mp_config_table *mc,
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u32 featureflag);
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void smp_write_processors(struct mp_config_table *mc);
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void smp_write_ioapic(struct mp_config_table *mc,
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u8 id, u8 ver, u32 apicaddr);
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u8 id, u8 ver, void *apicaddr);
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void smp_write_intsrc(struct mp_config_table *mc,
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u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq,
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u8 dstapic, u8 dstirq);
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@ -42,7 +42,7 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
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/* Set up EBDA */
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memset((void *)(ebda_segment << 4), 0, ebda_size);
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write16((ebda_segment << 4), (ebda_size >> 10));
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write16((void*)(ebda_segment << 4), (ebda_size >> 10));
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}
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void setup_default_ebda(void)
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@ -22,19 +22,19 @@
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#include <console/console.h>
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#include <cpu/x86/lapic.h>
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u32 io_apic_read(u32 ioapic_base, u32 reg)
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u32 io_apic_read(void *ioapic_base, u32 reg)
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{
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write32(ioapic_base, reg);
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return read32(ioapic_base + 0x10);
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}
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void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
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void io_apic_write(void *ioapic_base, u32 reg, u32 value)
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{
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write32(ioapic_base, reg);
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write32(ioapic_base + 0x10, value);
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}
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static int ioapic_interrupt_count(int ioapic_base)
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static int ioapic_interrupt_count(void *ioapic_base)
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{
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/* Read the available number of interrupts. */
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int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
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@ -48,12 +48,12 @@ static int ioapic_interrupt_count(int ioapic_base)
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return ioapic_interrupts;
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}
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void clear_ioapic(u32 ioapic_base)
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void clear_ioapic(void *ioapic_base)
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{
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u32 low, high;
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u32 i, ioapic_interrupts;
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printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
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printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base);
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ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
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@ -74,12 +74,12 @@ void clear_ioapic(u32 ioapic_base)
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}
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}
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void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
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void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
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{
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u32 bsp_lapicid = lapicid();
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int i;
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printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
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printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
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ioapic_base);
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printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
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bsp_lapicid);
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@ -99,7 +99,7 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
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}
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static void load_vectors(u32 ioapic_base)
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static void load_vectors(void *ioapic_base)
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{
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u32 bsp_lapicid = lapicid();
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u32 low, high;
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@ -146,7 +146,7 @@ static void load_vectors(u32 ioapic_base)
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}
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}
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void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
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void setup_ioapic(void *ioapic_base, u8 ioapic_id)
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{
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set_ioapic_id(ioapic_base, ioapic_id);
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load_vectors(ioapic_base);
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@ -9,46 +9,46 @@
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* Functions for accessing PCI configuration space with mmconf accesses
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*/
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#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) \
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(CONFIG_MMCONF_BASE_ADDRESS |\
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(((SEGBUS) & 0xFFF) << 20) |\
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(((DEVFN) & 0xFF) << 12) |\
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((WHERE) & 0xFFF))
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#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \
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((void *)((CONFIG_MMCONF_BASE_ADDRESS |\
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(((SEGBUS) & 0xFFF) << 20) |\
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(((DEVFN) & 0xFF) << 12) |\
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((WHERE) & 0xFFF)) & ~MASK))
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static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
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int where)
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{
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return (read8(PCI_MMIO_ADDR(bus, devfn, where)));
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return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
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}
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static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
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int where)
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{
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return (read16(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
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return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
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}
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static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
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int where)
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{
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return (read32(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
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return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
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}
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static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
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int where, uint8_t value)
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{
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write8(PCI_MMIO_ADDR(bus, devfn, where), value);
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write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
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}
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static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
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int where, uint16_t value)
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{
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write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value);
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write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
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}
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static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
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int where, uint32_t value)
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{
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write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value);
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write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
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}
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const struct pci_bus_operations pci_ops_mmconf = {
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@ -30,7 +30,7 @@
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#define HDA_ICII_BUSY (1 << 0)
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#define HDA_ICII_VALID (1 << 1)
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static int set_bits(u32 port, u32 mask, u32 val)
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static int set_bits(void *port, u32 mask, u32 val)
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{
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u32 reg32;
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int count;
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@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
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return 0;
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}
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static int codec_detect(u32 base)
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static int codec_detect(u8 *base)
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{
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u32 reg32;
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int count;
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@ -136,7 +136,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
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* no response would imply that the codec is non-operative
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*/
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static int wait_for_ready(u32 base)
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static int wait_for_ready(u8 *base)
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{
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/* Use a 50 usec timeout - the Linux kernel uses the
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* same duration */
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@ -159,14 +159,15 @@ static int wait_for_ready(u32 base)
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* is non-operative
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*/
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static int wait_for_valid(u32 base)
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static int wait_for_valid(u8 *base)
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{
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/* Use a 50 usec timeout - the Linux kernel uses the
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* same duration */
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int timeout = 25;
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write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY);
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write32(base + HDA_ICII_REG,
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HDA_ICII_VALID | HDA_ICII_BUSY);
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while (timeout--) {
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udelay(1);
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}
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@ -182,7 +183,7 @@ static int wait_for_valid(u32 base)
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return -1;
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}
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static void codec_init(struct device *dev, u32 base, int addr)
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static void codec_init(struct device *dev, u8 *base, int addr)
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{
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u32 reg32;
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const u32 *verb;
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@ -226,7 +227,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
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printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
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}
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static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
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static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
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{
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int i;
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@ -238,7 +239,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
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void azalia_audio_init(struct device *dev)
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{
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u32 base;
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u8 *base;
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struct resource *res;
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u32 codec_mask;
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@ -248,8 +249,8 @@ void azalia_audio_init(struct device *dev)
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// NOTE this will break as soon as the azalia_audio get's a bar above
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// 4G. Is there anything we can do about it?
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base = (u32) res->base;
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printk(BIOS_DEBUG, "azalia_audio: base = %08x\n", (u32) base);
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base = res2mmio(res, 0, 0);
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printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
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codec_mask = codec_detect(base);
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if (codec_mask) {
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@ -80,7 +80,7 @@ static void setup_rombios(void)
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memcpy((void *)0xfffd9, &ident, 7);
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/* system model: IBM-AT */
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write8(0xffffe, 0xfc);
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write8((void *)0xffffe, 0xfc);
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}
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static int (*intXX_handler[256])(void) = { NULL };
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@ -104,7 +104,7 @@ struct fb_info_aty {
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struct fb_info_aty *next;
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unsigned long ati_regbase_phys;
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#endif
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unsigned long ati_regbase;
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u8 *ati_regbase;
|
||||
#if 0
|
||||
unsigned long frame_buffer_phys;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@ struct fb_fix_screeninfo {
|
|||
u16 ypanstep; /* zero if no hardware panning */
|
||||
u16 ywrapstep; /* zero if no hardware ywrap */
|
||||
u32 line_length; /* length of a line in bytes */
|
||||
unsigned long mmio_start; /* Start of Memory Mapped I/O */
|
||||
u8 *mmio_start; /* Start of Memory Mapped I/O */
|
||||
/* (physical address) */
|
||||
u32 mmio_len; /* Length of Memory Mapped I/O */
|
||||
u32 accel; /* Type of acceleration available */
|
||||
|
|
|
|||
|
|
@ -537,13 +537,13 @@ static void ati_ragexl_init(struct device *dev)
|
|||
#endif /* CONFIG_CONSOLE_BTEXT */
|
||||
|
||||
#if USE_AUX_REG==0
|
||||
info->ati_regbase = res->base+0x7ff000+0xc00;
|
||||
info->ati_regbase = res2mmio(res, 0x7ff000+0xc00, 0);
|
||||
#else
|
||||
/* Fix this to look for the correct index. */
|
||||
//if (dev->resource_list && dev->resource_list->next)
|
||||
res = dev->resource_list->next->next;
|
||||
if(res->flags & IORESOURCE_MEM) {
|
||||
info->ati_regbase = res->base+0x400; //using auxiliary register
|
||||
info->ati_regbase = res2mmio(res, 0x400, 0); //using auxiliary register
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -553,7 +553,7 @@ static void ati_ragexl_init(struct device *dev)
|
|||
#endif
|
||||
|
||||
#if 0
|
||||
printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
|
||||
printk(BIOS_DEBUG, "ati_regbase = 0x%p, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
|
||||
#endif
|
||||
|
||||
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ typedef struct drivers_generic_ioapic_config {
|
|||
u8 irq_on_fsb;
|
||||
u8 enable_virtual_wire;
|
||||
u8 have_isa_interrupts;
|
||||
u32 base;
|
||||
void *base;
|
||||
} ioapic_config_t;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ static void ioapic_init(struct device *dev)
|
|||
u32 bsp_lapicid = lapicid();
|
||||
u32 low, high;
|
||||
u32 i, ioapic_interrupts;
|
||||
u32 ioapic_base;
|
||||
void *ioapic_base;
|
||||
u8 ioapic_id;
|
||||
|
||||
if (!dev->enabled || !config)
|
||||
|
|
@ -27,7 +27,7 @@ static void ioapic_init(struct device *dev)
|
|||
ioapic_base = config->base;
|
||||
ioapic_id = config->apicid;
|
||||
|
||||
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
|
||||
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
|
||||
ioapic_base);
|
||||
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
|
||||
bsp_lapicid);
|
||||
|
|
@ -93,7 +93,7 @@ static void ioapic_read_resources(struct device *dev)
|
|||
struct resource *res;
|
||||
|
||||
res = new_resource(dev, 0);
|
||||
res->base = config->base;
|
||||
res->base = (resource_t)(uintptr_t)config->base;
|
||||
res->size = 0x1000;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#include "i915_reg.h"
|
||||
#include "edid.h"
|
||||
|
||||
static void wait_rdy(u32 mmio)
|
||||
static void wait_rdy(u8 *mmio)
|
||||
{
|
||||
unsigned try = 100;
|
||||
|
||||
|
|
@ -37,7 +37,7 @@ static void wait_rdy(u32 mmio)
|
|||
}
|
||||
}
|
||||
|
||||
void intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
|
||||
void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
void intel_gmbus_read_edid(u32 gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);
|
||||
void intel_gmbus_read_edid(u8 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
|
|||
int loop = 0;
|
||||
|
||||
do {
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
/* Stop when the transaction is finished */
|
||||
if (ctrl & DBGP_DONE)
|
||||
break;
|
||||
|
|
@ -92,7 +92,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
|
|||
/* Now that we have observed the completed transaction,
|
||||
* clear the done bit.
|
||||
*/
|
||||
write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
|
||||
write32(&ehci_debug->control, ctrl | DBGP_DONE);
|
||||
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
|
||||
}
|
||||
|
||||
|
|
@ -122,10 +122,10 @@ host_retry:
|
|||
if (loop == 1 || host_retries > 1)
|
||||
dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
|
||||
loop, host_retries, ctrl | DBGP_GO);
|
||||
write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
|
||||
write32(&ehci_debug->control, ctrl | DBGP_GO);
|
||||
ret = dbgp_wait_until_complete(ehci_debug);
|
||||
rd_ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
rd_pids = read32((unsigned long)&ehci_debug->pids);
|
||||
rd_ctrl = read32(&ehci_debug->control);
|
||||
rd_pids = read32(&ehci_debug->pids);
|
||||
|
||||
if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
|
||||
ctrl_prev = rd_ctrl;
|
||||
|
|
@ -184,8 +184,8 @@ static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int
|
|||
lo |= bytes[i] << (8*i);
|
||||
for (; i < 8 && i < size; i++)
|
||||
hi |= bytes[i] << (8*(i - 4));
|
||||
write32((unsigned long)&ehci_debug->data03, lo);
|
||||
write32((unsigned long)&ehci_debug->data47, hi);
|
||||
write32(&ehci_debug->data03, lo);
|
||||
write32(&ehci_debug->data47, hi);
|
||||
}
|
||||
|
||||
static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
|
||||
|
|
@ -194,8 +194,8 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
|
|||
u32 lo, hi;
|
||||
int i;
|
||||
|
||||
lo = read32((unsigned long)&ehci_debug->data03);
|
||||
hi = read32((unsigned long)&ehci_debug->data47);
|
||||
lo = read32(&ehci_debug->data03);
|
||||
hi = read32(&ehci_debug->data47);
|
||||
for (i = 0; i < 4 && i < size; i++)
|
||||
bytes[i] = (lo >> (8*i)) & 0xff;
|
||||
for (; i < 8 && i < size; i++)
|
||||
|
|
@ -205,9 +205,9 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
|
|||
#if CONFIG_DEBUG_USBDEBUG
|
||||
static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
|
||||
{
|
||||
u32 ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
u32 lo = read32((unsigned long)&ehci_debug->data03);
|
||||
u32 hi = read32((unsigned long)&ehci_debug->data47);
|
||||
u32 ctrl = read32(&ehci_debug->control);
|
||||
u32 lo = read32(&ehci_debug->data03);
|
||||
u32 hi = read32(&ehci_debug->data47);
|
||||
int len = DBGP_LEN(ctrl);
|
||||
if (len) {
|
||||
int i;
|
||||
|
|
@ -233,13 +233,13 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *p
|
|||
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
|
||||
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
|
||||
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
ctrl = DBGP_LEN_UPDATE(ctrl, size);
|
||||
ctrl |= DBGP_OUT;
|
||||
|
||||
dbgp_set_data(ehci_debug, bytes, size);
|
||||
write32((unsigned long)&ehci_debug->address, addr);
|
||||
write32((unsigned long)&ehci_debug->pids, pids);
|
||||
write32(&ehci_debug->address, addr);
|
||||
write32(&ehci_debug->pids, pids);
|
||||
|
||||
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
|
||||
|
||||
|
|
@ -264,12 +264,12 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
|
|||
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
|
||||
pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
|
||||
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
ctrl = DBGP_LEN_UPDATE(ctrl, size);
|
||||
ctrl &= ~DBGP_OUT;
|
||||
|
||||
write32((unsigned long)&ehci_debug->address, addr);
|
||||
write32((unsigned long)&ehci_debug->pids, pids);
|
||||
write32(&ehci_debug->address, addr);
|
||||
write32(&ehci_debug->pids, pids);
|
||||
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
|
@ -324,14 +324,14 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
|
|||
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
|
||||
pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
|
||||
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
|
||||
ctrl |= DBGP_OUT;
|
||||
|
||||
/* Setup stage */
|
||||
dbgp_set_data(ehci_debug, &req, sizeof(req));
|
||||
write32((unsigned long)&ehci_debug->address, addr);
|
||||
write32((unsigned long)&ehci_debug->pids, pids);
|
||||
write32(&ehci_debug->address, addr);
|
||||
write32(&ehci_debug->pids, pids);
|
||||
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
|
@ -344,7 +344,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
|
|||
|
||||
/* Status stage in opposite direction */
|
||||
pipe->pid = USB_PID_DATA1;
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
ctrl = DBGP_LEN_UPDATE(ctrl, 0);
|
||||
if (read) {
|
||||
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
|
||||
|
|
@ -354,7 +354,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
|
|||
ctrl &= ~DBGP_OUT;
|
||||
}
|
||||
|
||||
write32((unsigned long)&ehci_debug->pids, pids);
|
||||
write32(&ehci_debug->pids, pids);
|
||||
ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
|
||||
if (ret2 < 0)
|
||||
return ret2;
|
||||
|
|
@ -368,21 +368,21 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
|
|||
int loop;
|
||||
|
||||
/* Reset the usb debug port */
|
||||
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
|
||||
portsc = read32(&ehci_regs->port_status[port - 1]);
|
||||
portsc &= ~PORT_PE;
|
||||
portsc |= PORT_RESET;
|
||||
write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
|
||||
write32(&ehci_regs->port_status[port - 1], portsc);
|
||||
|
||||
dbgp_mdelay(HUB_ROOT_RESET_TIME);
|
||||
|
||||
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
|
||||
write32((unsigned long)&ehci_regs->port_status[port - 1],
|
||||
portsc = read32(&ehci_regs->port_status[port - 1]);
|
||||
write32(&ehci_regs->port_status[port - 1],
|
||||
portsc & ~(PORT_RWC_BITS | PORT_RESET));
|
||||
|
||||
loop = 100;
|
||||
do {
|
||||
dbgp_mdelay(1);
|
||||
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
|
||||
portsc = read32(&ehci_regs->port_status[port - 1]);
|
||||
} while ((portsc & PORT_RESET) && (--loop > 0));
|
||||
|
||||
/* Device went away? */
|
||||
|
|
@ -407,7 +407,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
|
|||
|
||||
for (reps = 0; reps < 3; reps++) {
|
||||
dbgp_mdelay(100);
|
||||
status = read32((unsigned long)&ehci_regs->status);
|
||||
status = read32(&ehci_regs->status);
|
||||
if (status & STS_PCD) {
|
||||
ret = ehci_reset_port(ehci_regs, port);
|
||||
if (ret == 0)
|
||||
|
|
@ -440,7 +440,7 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
|
|||
|
||||
ehci_caps = (struct ehci_caps *)ehci_bar;
|
||||
ehci_regs = (struct ehci_regs *)(ehci_bar +
|
||||
HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
|
||||
HC_LENGTH(read32(&ehci_caps->hc_capbase)));
|
||||
|
||||
struct ehci_dbg_port *ehci_debug = info->ehci_debug;
|
||||
|
||||
|
|
@ -453,7 +453,7 @@ try_next_time:
|
|||
port_map_tried = 0;
|
||||
|
||||
try_next_port:
|
||||
hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
|
||||
hcs_params = read32(&ehci_caps->hcs_params);
|
||||
debug_port = HCS_DEBUG_PORT(hcs_params);
|
||||
n_ports = HCS_N_PORTS(hcs_params);
|
||||
|
||||
|
|
@ -461,7 +461,7 @@ try_next_port:
|
|||
dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
|
||||
|
||||
for (i = 1; i <= n_ports; i++) {
|
||||
portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
|
||||
portsc = read32(&ehci_regs->port_status[i-1]);
|
||||
dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
|
||||
}
|
||||
|
||||
|
|
@ -474,15 +474,15 @@ try_next_port:
|
|||
}
|
||||
|
||||
/* Wait until the controller is halted */
|
||||
status = read32((unsigned long)&ehci_regs->status);
|
||||
status = read32(&ehci_regs->status);
|
||||
if (!(status & STS_HALT)) {
|
||||
cmd = read32((unsigned long)&ehci_regs->command);
|
||||
cmd = read32(&ehci_regs->command);
|
||||
cmd &= ~CMD_RUN;
|
||||
write32((unsigned long)&ehci_regs->command, cmd);
|
||||
write32(&ehci_regs->command, cmd);
|
||||
loop = 100;
|
||||
do {
|
||||
dbgp_mdelay(10);
|
||||
status = read32((unsigned long)&ehci_regs->status);
|
||||
status = read32(&ehci_regs->status);
|
||||
} while (!(status & STS_HALT) && (--loop > 0));
|
||||
if (status & STS_HALT)
|
||||
dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
|
||||
|
|
@ -492,12 +492,12 @@ try_next_port:
|
|||
|
||||
loop = 100;
|
||||
/* Reset the EHCI controller */
|
||||
cmd = read32((unsigned long)&ehci_regs->command);
|
||||
cmd = read32(&ehci_regs->command);
|
||||
cmd |= CMD_RESET;
|
||||
write32((unsigned long)&ehci_regs->command, cmd);
|
||||
write32(&ehci_regs->command, cmd);
|
||||
do {
|
||||
dbgp_mdelay(10);
|
||||
cmd = read32((unsigned long)&ehci_regs->command);
|
||||
cmd = read32(&ehci_regs->command);
|
||||
} while ((cmd & CMD_RESET) && (--loop > 0));
|
||||
|
||||
if(!loop) {
|
||||
|
|
@ -509,25 +509,25 @@ try_next_port:
|
|||
}
|
||||
|
||||
/* Claim ownership, but do not enable yet */
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
ctrl |= DBGP_OWNER;
|
||||
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
|
||||
write32((unsigned long)&ehci_debug->control, ctrl);
|
||||
write32(&ehci_debug->control, ctrl);
|
||||
|
||||
/* Start EHCI controller */
|
||||
cmd = read32((unsigned long)&ehci_regs->command);
|
||||
cmd = read32(&ehci_regs->command);
|
||||
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
|
||||
cmd |= CMD_RUN;
|
||||
write32((unsigned long)&ehci_regs->command, cmd);
|
||||
write32(&ehci_regs->command, cmd);
|
||||
|
||||
/* Ensure everything is routed to the EHCI */
|
||||
write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
|
||||
write32(&ehci_regs->configured_flag, FLAG_CF);
|
||||
|
||||
/* Wait until the controller is no longer halted */
|
||||
loop = 10;
|
||||
do {
|
||||
dbgp_mdelay(10);
|
||||
status = read32((unsigned long)&ehci_regs->status);
|
||||
status = read32(&ehci_regs->status);
|
||||
} while ((status & STS_HALT) && (--loop > 0));
|
||||
|
||||
if(!loop) {
|
||||
|
|
@ -546,13 +546,13 @@ try_next_port:
|
|||
|
||||
|
||||
/* Enable the debug port */
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
ctrl |= DBGP_CLAIM;
|
||||
write32((unsigned long)&ehci_debug->control, ctrl);
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
write32(&ehci_debug->control, ctrl);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
|
||||
dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
|
||||
write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
|
||||
write32(&ehci_debug->control, ctrl & ~DBGP_CLAIM);
|
||||
ret = -4;
|
||||
goto err;
|
||||
}
|
||||
|
|
@ -560,9 +560,9 @@ try_next_port:
|
|||
|
||||
#if 0
|
||||
/* Completely transfer the debug device to the debug controller */
|
||||
portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
|
||||
portsc = read32(&ehci_regs->port_status[debug_port - 1]);
|
||||
portsc &= ~PORT_PE;
|
||||
write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
|
||||
write32(&ehci_regs->port_status[debug_port - 1], portsc);
|
||||
#endif
|
||||
|
||||
dbgp_mdelay(100);
|
||||
|
|
@ -577,9 +577,9 @@ try_next_port:
|
|||
return 0;
|
||||
err:
|
||||
/* Things didn't work so remove my claim */
|
||||
ctrl = read32((unsigned long)&ehci_debug->control);
|
||||
ctrl = read32(&ehci_debug->control);
|
||||
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
|
||||
write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
|
||||
write32(&ehci_debug->control, ctrl);
|
||||
//return ret;
|
||||
|
||||
next_debug_port:
|
||||
|
|
|
|||
|
|
@ -103,13 +103,13 @@ void pci_ehci_read_resources(struct device *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
|
||||
u8 *pci_ehci_base_regs(pci_devfn_t sdev)
|
||||
{
|
||||
#ifdef __SIMPLE_DEVICE__
|
||||
unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
|
||||
u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
|
||||
#else
|
||||
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
|
||||
unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
|
||||
u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
|
||||
#endif
|
||||
return base + HC_LENGTH(read32(base));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
|
||||
|
||||
pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
|
||||
unsigned long pci_ehci_base_regs(pci_devfn_t dev);
|
||||
u8 *pci_ehci_base_regs(pci_devfn_t dev);
|
||||
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
|
||||
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
|
||||
|
||||
|
|
|
|||
|
|
@ -74,4 +74,10 @@ extern void search_global_resources(
|
|||
#define RESOURCE_TYPE_MAX 20
|
||||
extern const char *resource_type(struct resource *resource);
|
||||
|
||||
static inline void *res2mmio(struct resource *res, unsigned long offset,
|
||||
unsigned long mask)
|
||||
{
|
||||
return (void *)(uintptr_t)((res->base + offset) & ~mask);
|
||||
}
|
||||
|
||||
#endif /* DEVICE_RESOURCE_H */
|
||||
|
|
|
|||
|
|
@ -155,11 +155,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
|
|||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
return read8(step->reg);
|
||||
return read8((u8 *)step->reg);
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
return read16(step->reg);
|
||||
return read16((u16 *)step->reg);
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
return read32(step->reg);
|
||||
return read32((u32 *)step->reg);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -170,13 +170,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx)
|
|||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
write8(step->reg, step->value);
|
||||
write8((u8 *)step->reg, step->value);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
write16(step->reg, step->value);
|
||||
write16((u16 *)step->reg, step->value);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
write32(step->reg, step->value);
|
||||
write32((u32 *)step->reg, step->value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
|
|||
/* I/O APICs: APIC ID Version State Address */
|
||||
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword &= 0xFFFFFFF0;
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
|
|||
dword |= (pm_ioread(0x35) & 0xFF) << 8;
|
||||
dword |= (pm_ioread(0x36) & 0xFF) << 16;
|
||||
dword |= (pm_ioread(0x37) & 0xFF) << 24;
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb600,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
|
|||
u32 apicid_sb700;
|
||||
u32 apicid_rd890;
|
||||
device_t dev;
|
||||
u32 dword;
|
||||
u8 *dword;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
|
@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
|
|||
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
||||
if (dev) {
|
||||
/* Set sb700 IOAPIC ID */
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
dword = (u8 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
|
||||
|
||||
/*
|
||||
|
|
@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v)
|
|||
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
|
||||
if (dev) {
|
||||
pci_write_config32(dev, 0xF8, 0x1);
|
||||
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
|
||||
dword = (u8 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
|
||||
smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -52,8 +52,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
u8 byte;
|
||||
|
||||
|
|
|
|||
|
|
@ -60,7 +60,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
outb(byte, 0xC00);
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
outb(byte, 0xC00);
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
|
|
|
|||
|
|
@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Intialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
|
@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
|
|||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb600,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -60,14 +62,16 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
@ -56,14 +56,16 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -79,14 +81,16 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
u8 byte;
|
||||
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -107,11 +107,11 @@ static void *smp_write_config_table(void *v)
|
|||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
|
||||
u32 dword;
|
||||
u8 *dword;
|
||||
u8 byte;
|
||||
|
||||
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword &= 0xFFFFFFF0;
|
||||
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
|
||||
/* Set IO APIC ID onto IO_APIC_ID */
|
||||
write32 (dword, 0x00);
|
||||
write32 (dword + 0x10, IO_APIC_ID << 24);
|
||||
|
|
|
|||
|
|
@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
u8 byte;
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &isa_bus);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
|
||||
|
||||
/* Legacy Interrupts */
|
||||
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
@ -134,7 +134,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
/* 8131 apic 4 */
|
||||
|
|
@ -142,7 +143,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
|
||||
smp_write_ioapic(mc, apicid_8131_2, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
u8 byte;
|
||||
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -93,9 +93,9 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
outb(byte, 0xC00);
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
|
|||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11,
|
||||
res->base);
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
|
||||
/* Initialize interrupt mapping. */
|
||||
|
|
|
|||
|
|
@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -91,13 +91,13 @@ chip northbridge/intel/i5000
|
|||
register "have_isa_interrupts" = "1"
|
||||
register "irq_on_fsb" = "1"
|
||||
register "enable_virtual_wire" = "1"
|
||||
register "base" = "0xfec00000"
|
||||
register "base" = "(void *)0xfec00000"
|
||||
device ioapic 8 on end
|
||||
end
|
||||
|
||||
chip drivers/generic/ioapic
|
||||
register "irq_on_fsb" = "1"
|
||||
register "base" = "0xfec80000"
|
||||
register "base" = "(void *)0xfec80000"
|
||||
device ioapic 9 on end
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ static void early_config(void)
|
|||
u32 gcs, rpc, fd;
|
||||
|
||||
/* Enable RCBA */
|
||||
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
|
||||
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
|
||||
|
||||
/* Disable watchdog */
|
||||
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
|
||||
|
|
@ -138,7 +138,7 @@ void main(unsigned long bist)
|
|||
smbus_write_byte(0x6f, 0x08, 0x06);
|
||||
smbus_write_byte(0x6f, 0x09, 0x00);
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
|
||||
i5000_fbdimm_init();
|
||||
smbus_write_byte(0x69, 0x01, 0x01);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
|
|
|
|||
|
|
@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -62,7 +62,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
|
||||
/* Initialize interrupt mapping. */
|
||||
|
|
|
|||
|
|
@ -56,7 +56,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res)
|
||||
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
|
||||
smp_write_ioapic(mc, apicid_mcp55, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
|
||||
pci_write_config32(dev, 0x7c, 0x00000000);
|
||||
pci_write_config32(dev, 0x80, 0x11002009);
|
||||
|
|
|
|||
|
|
@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE);
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, VIO_APIC_VADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, (void*)K8T890_APIC_BASE);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
|
|||
/* I/O APICs: APIC ID Version State Address */
|
||||
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword &= 0xFFFFFFF0;
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
|
|||
|
||||
ioapic_id = 2;
|
||||
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* Legacy Interrupts */
|
||||
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
|
|||
|
||||
ioapic_id = 2;
|
||||
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* Legacy Interrupts */
|
||||
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
|
|||
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword &= 0xFFFFFFF0;
|
||||
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
|
|
|
|||
|
|
@ -41,7 +41,9 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base);
|
||||
smp_write_ioapic(mc, apicid_bcm5785[i],
|
||||
0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &isa_bus);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
|
||||
|
||||
/* Legacy Interrupts */
|
||||
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_sis966, 0x11, res->base);
|
||||
smp_write_ioapic(mc, apicid_sis966, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
|
||||
dword = 0x43c6c643;
|
||||
|
|
|
|||
|
|
@ -57,7 +57,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
|
||||
smp_write_ioapic(mc, apicid_mcp55, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
/* set up the interrupt registers of mcp55 */
|
||||
pci_write_config32(dev, 0x7c, 0xc643c643);
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
u8 byte;
|
||||
|
||||
|
|
|
|||
|
|
@ -40,8 +40,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Intialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
|
@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
|
|||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
|
|
|
|||
|
|
@ -102,15 +102,15 @@ void mainboard_romstage_entry(unsigned long bist)
|
|||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = DEFAULT_RCBA,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -81,15 +81,15 @@ void main(unsigned long bist)
|
|||
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = CONFIG_HPET_ADDRESS,
|
||||
.rcba = DEFAULT_RCBABASE,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBABASE,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.thermalbase = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -111,15 +111,15 @@ void mainboard_romstage_entry(unsigned long bist)
|
|||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = DEFAULT_RCBA,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -122,15 +122,15 @@ void main(unsigned long bist)
|
|||
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = CONFIG_HPET_ADDRESS,
|
||||
.rcba = DEFAULT_RCBABASE,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBABASE,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.thermalbase = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -81,15 +81,15 @@ void mainboard_romstage_entry(unsigned long bist)
|
|||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = DEFAULT_RCBA,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -81,15 +81,15 @@ void main(unsigned long bist)
|
|||
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = CONFIG_HPET_ADDRESS,
|
||||
.rcba = DEFAULT_RCBABASE,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBABASE,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.thermalbase = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -122,15 +122,15 @@ void mainboard_romstage_entry(unsigned long bist)
|
|||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = DEFAULT_RCBA,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -137,15 +137,15 @@ void mainboard_romstage_entry(unsigned long bist)
|
|||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = DEFAULT_RCBA,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -122,15 +122,15 @@ void main(unsigned long bist)
|
|||
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = CONFIG_HPET_ADDRESS,
|
||||
.rcba = DEFAULT_RCBABASE,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBABASE,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.thermalbase = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -93,9 +93,9 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
outb(byte, 0xC00);
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8131_1, 0x20,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8131_2, 0x20,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -67,7 +67,8 @@ static void *smp_write_config_table(void *v)
|
|||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
|
||||
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -68,7 +68,8 @@ static void *smp_write_config_table(void *v)
|
|||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base);
|
||||
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
|
|||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
|
|||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
|
|||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
ioapic_id = 2;
|
||||
smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, ioapic_id, 0x20, VIO_APIC_VADDR);
|
||||
|
||||
/* Legacy Interrupts */
|
||||
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* Legacy IOAPIC #2 */
|
||||
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
@ -67,7 +67,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x03, 0x11, res->base);
|
||||
smp_write_ioapic(mc, 0x03, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
/* 8131-2 apic #4 */
|
||||
|
|
@ -75,7 +76,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x11, res->base);
|
||||
smp_write_ioapic(mc, 0x04, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* Legacy IOAPIC #2 */
|
||||
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
@ -66,7 +66,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x03, 0x11, res->base);
|
||||
smp_write_ioapic(mc, 0x03, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
/* 8131-2 apic #4 */
|
||||
|
|
@ -74,7 +75,8 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x11, res->base);
|
||||
smp_write_ioapic(mc, 0x04, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
|
|||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
|
|
|
|||
|
|
@ -71,15 +71,15 @@ void mainboard_romstage_entry(unsigned long bist)
|
|||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = DEFAULT_RCBA,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &isa_bus);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
|
||||
|
||||
/* Legacy Interrupts */
|
||||
|
||||
|
|
|
|||
|
|
@ -67,14 +67,14 @@ static void *smp_write_config_table(void *v)
|
|||
uint32_t pin, route;
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
unsigned long rcba;
|
||||
u8 *rcba;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
|
||||
res = find_resource(dev, RCBA);
|
||||
if (!res) {
|
||||
return NULL;
|
||||
}
|
||||
rcba = res->base;
|
||||
rcba = res2mmio(res, 0, 0);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
|
|
@ -121,7 +121,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ static void early_config(void)
|
|||
u32 gcs, rpc, fd;
|
||||
|
||||
/* Enable RCBA */
|
||||
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
|
||||
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
|
||||
|
||||
/* Disable watchdog */
|
||||
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
|
||||
|
|
|
|||
|
|
@ -135,15 +135,15 @@ void main(unsigned long bist)
|
|||
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = DEFAULT_MCHBAR,
|
||||
.dmibar = DEFAULT_DMIBAR,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = CONFIG_HPET_ADDRESS,
|
||||
.rcba = DEFAULT_RCBABASE,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBABASE,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.thermalbase = 0xfed08000,
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
|
||||
static void interrupt_routing_config(void)
|
||||
{
|
||||
u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf;
|
||||
u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf);
|
||||
|
||||
/*
|
||||
* Initialize Interrupt Routings for each device in ilb_base_address.
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_processors(mc);
|
||||
mptable_write_buses(mc, NULL, &isa_bus);
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
|
|||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
|
@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -60,14 +62,16 @@ static void *smp_write_config_table(void *v)
|
|||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue