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x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
This commit is contained in:
Kevin Paul Herbert 2014-12-24 18:43:20 -08:00 committed by Alexandru Gagniuc
parent 4b10dec1a6
commit bde6d309df
354 changed files with 1900 additions and 1684 deletions
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2
src/arch/x86/boot/mpspec.c
View File

@ -222,7 +222,7 @@ static void smp_write_bus(struct mp_config_table *mc,
* APIC Flags:EN, Address * APIC Flags:EN, Address
*/ */
void smp_write_ioapic(struct mp_config_table *mc, void smp_write_ioapic(struct mp_config_table *mc,
u8 id, u8 ver, u32 apicaddr) u8 id, u8 ver, void *apicaddr)
{ {
struct mpc_config_ioapic *mpc; struct mpc_config_ioapic *mpc;
mpc = smp_next_mpc_entry(mc); mpc = smp_next_mpc_entry(mc);

6
src/arch/x86/include/arch/ebda.h
View File

@ -23,9 +23,9 @@
#define __ARCH_EBDA_H #define __ARCH_EBDA_H
#define X86_BDA_SIZE 0x200 #define X86_BDA_SIZE 0x200
#define X86_BDA_BASE 0x400 #define X86_BDA_BASE (void *)0x400
#define X86_EBDA_SEGMENT 0x40e #define X86_EBDA_SEGMENT (void *)0x40e
#define X86_EBDA_LOWMEM 0x413 #define X86_EBDA_LOWMEM (void *)0x413
#define DEFAULT_EBDA_LOWMEM (1024 << 10) #define DEFAULT_EBDA_LOWMEM (1024 << 10)
#define DEFAULT_EBDA_SEGMENT 0xF600 #define DEFAULT_EBDA_SEGMENT 0xF600

12
src/arch/x86/include/arch/io.h
View File

@ -142,32 +142,32 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
); );
} }
static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
{ {
return *((volatile uint8_t *)(addr)); return *((volatile uint8_t *)(addr));
} }
static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
{ {
return *((volatile uint16_t *)(addr)); return *((volatile uint16_t *)(addr));
} }
static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
{ {
return *((volatile uint32_t *)(addr)); return *((volatile uint32_t *)(addr));
} }
static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
{ {
*((volatile uint8_t *)(addr)) = value; *((volatile uint8_t *)(addr)) = value;
} }
static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
{ {
*((volatile uint16_t *)(addr)) = value; *((volatile uint16_t *)(addr)) = value;
} }
static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
{ {
*((volatile uint32_t *)(addr)) = value; *((volatile uint32_t *)(addr)) = value;
} }

11
src/arch/x86/include/arch/ioapic.h
View File

@ -21,6 +21,7 @@
#define __I386_ARCH_IOAPIC_H #define __I386_ARCH_IOAPIC_H
#define IO_APIC_ADDR 0xfec00000 #define IO_APIC_ADDR 0xfec00000
#define VIO_APIC_VADDR ((u8 *)IO_APIC_ADDR)
#define IO_APIC_INTERRUPTS 24 #define IO_APIC_INTERRUPTS 24
#ifndef __ACPI__ #ifndef __ACPI__
@ -42,11 +43,11 @@
#define SMI (2 << 8) #define SMI (2 << 8)
#define INT (1 << 8) #define INT (1 << 8)
u32 io_apic_read(u32 ioapic_base, u32 reg); u32 io_apic_read(void *ioapic_base, u32 reg);
void io_apic_write(u32 ioapic_base, u32 reg, u32 value); void io_apic_write(void *ioapic_base, u32 reg, u32 value);
void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void set_ioapic_id(void *ioapic_base, u8 ioapic_id);
void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(void *ioapic_base, u8 ioapic_id);
void clear_ioapic(u32 ioapic_base); void clear_ioapic(void *ioapic_base);
#endif #endif
#endif #endif

24
src/arch/x86/include/arch/pci_mmio_cfg.h
View File

@ -28,48 +28,48 @@
static inline __attribute__ ((always_inline)) static inline __attribute__ ((always_inline))
u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) u8 pcie_read_config8(pci_devfn_t dev, unsigned int where)
{ {
unsigned long addr; void *addr;
addr = DEFAULT_PCIEXBAR | dev | where; addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
return read8(addr); return read8(addr);
} }
static inline __attribute__ ((always_inline)) static inline __attribute__ ((always_inline))
u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) u16 pcie_read_config16(pci_devfn_t dev, unsigned int where)
{ {
unsigned long addr; void *addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~1); addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
return read16(addr); return read16(addr);
} }
static inline __attribute__ ((always_inline)) static inline __attribute__ ((always_inline))
u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) u32 pcie_read_config32(pci_devfn_t dev, unsigned int where)
{ {
unsigned long addr; void *addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~3); addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
return read32(addr); return read32(addr);
} }
static inline __attribute__ ((always_inline)) static inline __attribute__ ((always_inline))
void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
{ {
unsigned long addr; void *addr;
addr = DEFAULT_PCIEXBAR | dev | where; addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
write8(addr, value); write8(addr, value);
} }
static inline __attribute__ ((always_inline)) static inline __attribute__ ((always_inline))
void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
{ {
unsigned long addr; void *addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~1); addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
write16(addr, value); write16(addr, value);
} }
static inline __attribute__ ((always_inline)) static inline __attribute__ ((always_inline))
void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
{ {
unsigned long addr; void *addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~3); addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
write32(addr, value); write32(addr, value);
} }

4
src/arch/x86/include/arch/smp/mpspec.h
View File

@ -123,7 +123,7 @@ struct mpc_config_ioapic
u8 mpc_apicver; u8 mpc_apicver;
u8 mpc_flags; u8 mpc_flags;
#define MPC_APIC_USABLE 0x01 #define MPC_APIC_USABLE 0x01
u32 mpc_apicaddr; void *mpc_apicaddr;
} __attribute__((packed)); } __attribute__((packed));
struct mpc_config_intsrc struct mpc_config_intsrc
@ -260,7 +260,7 @@ void smp_write_processor(struct mp_config_table *mc,
u32 featureflag); u32 featureflag);
void smp_write_processors(struct mp_config_table *mc); void smp_write_processors(struct mp_config_table *mc);
void smp_write_ioapic(struct mp_config_table *mc, void smp_write_ioapic(struct mp_config_table *mc,
u8 id, u8 ver, u32 apicaddr); u8 id, u8 ver, void *apicaddr);
void smp_write_intsrc(struct mp_config_table *mc, void smp_write_intsrc(struct mp_config_table *mc,
u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq, u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq,
u8 dstapic, u8 dstirq); u8 dstapic, u8 dstirq);

2
src/arch/x86/lib/ebda.c
View File

@ -42,7 +42,7 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
/* Set up EBDA */ /* Set up EBDA */
memset((void *)(ebda_segment << 4), 0, ebda_size); memset((void *)(ebda_segment << 4), 0, ebda_size);
write16((ebda_segment << 4), (ebda_size >> 10)); write16((void*)(ebda_segment << 4), (ebda_size >> 10));
} }
void setup_default_ebda(void) void setup_default_ebda(void)

18
src/arch/x86/lib/ioapic.c
View File

@ -22,19 +22,19 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
u32 io_apic_read(u32 ioapic_base, u32 reg) u32 io_apic_read(void *ioapic_base, u32 reg)
{ {
write32(ioapic_base, reg); write32(ioapic_base, reg);
return read32(ioapic_base + 0x10); return read32(ioapic_base + 0x10);
} }
void io_apic_write(u32 ioapic_base, u32 reg, u32 value) void io_apic_write(void *ioapic_base, u32 reg, u32 value)
{ {
write32(ioapic_base, reg); write32(ioapic_base, reg);
write32(ioapic_base + 0x10, value); write32(ioapic_base + 0x10, value);
} }
static int ioapic_interrupt_count(int ioapic_base) static int ioapic_interrupt_count(void *ioapic_base)
{ {
/* Read the available number of interrupts. */ /* Read the available number of interrupts. */
int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
@ -48,12 +48,12 @@ static int ioapic_interrupt_count(int ioapic_base)
return ioapic_interrupts; return ioapic_interrupts;
} }
void clear_ioapic(u32 ioapic_base) void clear_ioapic(void *ioapic_base)
{ {
u32 low, high; u32 low, high;
u32 i, ioapic_interrupts; u32 i, ioapic_interrupts;
printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base);
ioapic_interrupts = ioapic_interrupt_count(ioapic_base); ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
@ -74,12 +74,12 @@ void clear_ioapic(u32 ioapic_base)
} }
} }
void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
{ {
u32 bsp_lapicid = lapicid(); u32 bsp_lapicid = lapicid();
int i; int i;
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
ioapic_base); ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
bsp_lapicid); bsp_lapicid);
@ -99,7 +99,7 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
} }
static void load_vectors(u32 ioapic_base) static void load_vectors(void *ioapic_base)
{ {
u32 bsp_lapicid = lapicid(); u32 bsp_lapicid = lapicid();
u32 low, high; u32 low, high;
@ -146,7 +146,7 @@ static void load_vectors(u32 ioapic_base)
} }
} }
void setup_ioapic(u32 ioapic_base, u8 ioapic_id) void setup_ioapic(void *ioapic_base, u8 ioapic_id)
{ {
set_ioapic_id(ioapic_base, ioapic_id); set_ioapic_id(ioapic_base, ioapic_id);
load_vectors(ioapic_base); load_vectors(ioapic_base);

18
src/arch/x86/lib/pci_ops_mmconf.c
View File

@ -9,46 +9,46 @@
* Functions for accessing PCI configuration space with mmconf accesses * Functions for accessing PCI configuration space with mmconf accesses
*/ */
#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) \ #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \
(CONFIG_MMCONF_BASE_ADDRESS |\ ((void *)((CONFIG_MMCONF_BASE_ADDRESS |\
(((SEGBUS) & 0xFFF) << 20) |\ (((SEGBUS) & 0xFFF) << 20) |\
(((DEVFN) & 0xFF) << 12) |\ (((DEVFN) & 0xFF) << 12) |\
((WHERE) & 0xFFF)) ((WHERE) & 0xFFF)) & ~MASK))
static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
int where) int where)
{ {
return (read8(PCI_MMIO_ADDR(bus, devfn, where))); return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
} }
static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
int where) int where)
{ {
return (read16(PCI_MMIO_ADDR(bus, devfn, where) & ~1)); return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
} }
static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
int where) int where)
{ {
return (read32(PCI_MMIO_ADDR(bus, devfn, where) & ~3)); return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
} }
static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
int where, uint8_t value) int where, uint8_t value)
{ {
write8(PCI_MMIO_ADDR(bus, devfn, where), value); write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
} }
static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
int where, uint16_t value) int where, uint16_t value)
{ {
write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value); write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
} }
static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
int where, uint32_t value) int where, uint32_t value)
{ {
write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value); write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
} }
const struct pci_bus_operations pci_ops_mmconf = { const struct pci_bus_operations pci_ops_mmconf = {

21
src/device/azalia_device.c
View File

@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1) #define HDA_ICII_VALID (1 << 1)
static int set_bits(u32 port, u32 mask, u32 val) static int set_bits(void *port, u32 mask, u32 val)
{ {
u32 reg32; u32 reg32;
int count; int count;
@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0; return 0;
} }
static int codec_detect(u32 base) static int codec_detect(u8 *base)
{ {
u32 reg32; u32 reg32;
int count; int count;
@ -136,7 +136,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative * no response would imply that the codec is non-operative
*/ */
static int wait_for_ready(u32 base) static int wait_for_ready(u8 *base)
{ {
/* Use a 50 usec timeout - the Linux kernel uses the /* Use a 50 usec timeout - the Linux kernel uses the
* same duration */ * same duration */
@ -159,14 +159,15 @@ static int wait_for_ready(u32 base)
* is non-operative * is non-operative
*/ */
static int wait_for_valid(u32 base) static int wait_for_valid(u8 *base)
{ {
/* Use a 50 usec timeout - the Linux kernel uses the /* Use a 50 usec timeout - the Linux kernel uses the
* same duration */ * same duration */
int timeout = 25; int timeout = 25;
write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY); write32(base + HDA_ICII_REG,
HDA_ICII_VALID | HDA_ICII_BUSY);
while (timeout--) { while (timeout--) {
udelay(1); udelay(1);
} }
@ -182,7 +183,7 @@ static int wait_for_valid(u32 base)
return -1; return -1;
} }
static void codec_init(struct device *dev, u32 base, int addr) static void codec_init(struct device *dev, u8 *base, int addr)
{ {
u32 reg32; u32 reg32;
const u32 *verb; const u32 *verb;
@ -226,7 +227,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
} }
static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{ {
int i; int i;
@ -238,7 +239,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
void azalia_audio_init(struct device *dev) void azalia_audio_init(struct device *dev)
{ {
u32 base; u8 *base;
struct resource *res; struct resource *res;
u32 codec_mask; u32 codec_mask;
@ -248,8 +249,8 @@ void azalia_audio_init(struct device *dev)
// NOTE this will break as soon as the azalia_audio get's a bar above // NOTE this will break as soon as the azalia_audio get's a bar above
// 4G. Is there anything we can do about it? // 4G. Is there anything we can do about it?
base = (u32) res->base; base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "azalia_audio: base = %08x\n", (u32) base); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
codec_mask = codec_detect(base); codec_mask = codec_detect(base);
if (codec_mask) { if (codec_mask) {

2
src/device/oprom/realmode/x86.c
View File

@ -80,7 +80,7 @@ static void setup_rombios(void)
memcpy((void *)0xfffd9, &ident, 7); memcpy((void *)0xfffd9, &ident, 7);
/* system model: IBM-AT */ /* system model: IBM-AT */
write8(0xffffe, 0xfc); write8((void *)0xffffe, 0xfc);
} }
static int (*intXX_handler[256])(void) = { NULL }; static int (*intXX_handler[256])(void) = { NULL };

2
src/drivers/ati/ragexl/atyfb.h
View File

@ -104,7 +104,7 @@ struct fb_info_aty {
struct fb_info_aty *next; struct fb_info_aty *next;
unsigned long ati_regbase_phys; unsigned long ati_regbase_phys;
#endif #endif
unsigned long ati_regbase; u8 *ati_regbase;
#if 0 #if 0
unsigned long frame_buffer_phys; unsigned long frame_buffer_phys;
#endif #endif

2
src/drivers/ati/ragexl/fb.h
View File

@ -124,7 +124,7 @@ struct fb_fix_screeninfo {
u16 ypanstep; /* zero if no hardware panning */ u16 ypanstep; /* zero if no hardware panning */
u16 ywrapstep; /* zero if no hardware ywrap */ u16 ywrapstep; /* zero if no hardware ywrap */
u32 line_length; /* length of a line in bytes */ u32 line_length; /* length of a line in bytes */
unsigned long mmio_start; /* Start of Memory Mapped I/O */ u8 *mmio_start; /* Start of Memory Mapped I/O */
/* (physical address) */ /* (physical address) */
u32 mmio_len; /* Length of Memory Mapped I/O */ u32 mmio_len; /* Length of Memory Mapped I/O */
u32 accel; /* Type of acceleration available */ u32 accel; /* Type of acceleration available */

6
src/drivers/ati/ragexl/xlinit.c
View File

@ -537,13 +537,13 @@ static void ati_ragexl_init(struct device *dev)
#endif /* CONFIG_CONSOLE_BTEXT */ #endif /* CONFIG_CONSOLE_BTEXT */
#if USE_AUX_REG==0 #if USE_AUX_REG==0
info->ati_regbase = res->base+0x7ff000+0xc00; info->ati_regbase = res2mmio(res, 0x7ff000+0xc00, 0);
#else #else
/* Fix this to look for the correct index. */ /* Fix this to look for the correct index. */
//if (dev->resource_list && dev->resource_list->next) //if (dev->resource_list && dev->resource_list->next)
res = dev->resource_list->next->next; res = dev->resource_list->next->next;
if(res->flags & IORESOURCE_MEM) { if(res->flags & IORESOURCE_MEM) {
info->ati_regbase = res->base+0x400; //using auxiliary register info->ati_regbase = res2mmio(res, 0x400, 0); //using auxiliary register
} }
#endif #endif
@ -553,7 +553,7 @@ static void ati_ragexl_init(struct device *dev)
#endif #endif
#if 0 #if 0
printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer); printk(BIOS_DEBUG, "ati_regbase = 0x%p, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
#endif #endif
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info); chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);

2
src/drivers/generic/ioapic/chip.h
View File

@ -27,7 +27,7 @@ typedef struct drivers_generic_ioapic_config {
u8 irq_on_fsb; u8 irq_on_fsb;
u8 enable_virtual_wire; u8 enable_virtual_wire;
u8 have_isa_interrupts; u8 have_isa_interrupts;
u32 base; void *base;
} ioapic_config_t; } ioapic_config_t;
#endif #endif

6
src/drivers/generic/ioapic/ioapic.c
View File

@ -18,7 +18,7 @@ static void ioapic_init(struct device *dev)
u32 bsp_lapicid = lapicid(); u32 bsp_lapicid = lapicid();
u32 low, high; u32 low, high;
u32 i, ioapic_interrupts; u32 i, ioapic_interrupts;
u32 ioapic_base; void *ioapic_base;
u8 ioapic_id; u8 ioapic_id;
if (!dev->enabled || !config) if (!dev->enabled || !config)
@ -27,7 +27,7 @@ static void ioapic_init(struct device *dev)
ioapic_base = config->base; ioapic_base = config->base;
ioapic_id = config->apicid; ioapic_id = config->apicid;
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
ioapic_base); ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
bsp_lapicid); bsp_lapicid);
@ -93,7 +93,7 @@ static void ioapic_read_resources(struct device *dev)
struct resource *res; struct resource *res;
res = new_resource(dev, 0); res = new_resource(dev, 0);
res->base = config->base; res->base = (resource_t)(uintptr_t)config->base;
res->size = 0x1000; res->size = 0x1000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }

4
src/drivers/intel/gma/edid.c
View File

@ -26,7 +26,7 @@
#include "i915_reg.h" #include "i915_reg.h"
#include "edid.h" #include "edid.h"
static void wait_rdy(u32 mmio) static void wait_rdy(u8 *mmio)
{ {
unsigned try = 100; unsigned try = 100;
@ -37,7 +37,7 @@ static void wait_rdy(u32 mmio)
} }
} }
void intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
{ {
int i; int i;

2
src/drivers/intel/gma/edid.h
View File

@ -1 +1 @@
void intel_gmbus_read_edid(u32 gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size); void intel_gmbus_read_edid(u8 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);

106
src/drivers/usb/ehci_debug.c
View File

@ -78,7 +78,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
int loop = 0; int loop = 0;
do { do {
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
/* Stop when the transaction is finished */ /* Stop when the transaction is finished */
if (ctrl & DBGP_DONE) if (ctrl & DBGP_DONE)
break; break;
@ -92,7 +92,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
/* Now that we have observed the completed transaction, /* Now that we have observed the completed transaction,
* clear the done bit. * clear the done bit.
*/ */
write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE); write32(&ehci_debug->control, ctrl | DBGP_DONE);
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl); return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
} }
@ -122,10 +122,10 @@ host_retry:
if (loop == 1 || host_retries > 1) if (loop == 1 || host_retries > 1)
dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n", dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
loop, host_retries, ctrl | DBGP_GO); loop, host_retries, ctrl | DBGP_GO);
write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO); write32(&ehci_debug->control, ctrl | DBGP_GO);
ret = dbgp_wait_until_complete(ehci_debug); ret = dbgp_wait_until_complete(ehci_debug);
rd_ctrl = read32((unsigned long)&ehci_debug->control); rd_ctrl = read32(&ehci_debug->control);
rd_pids = read32((unsigned long)&ehci_debug->pids); rd_pids = read32(&ehci_debug->pids);
if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) { if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
ctrl_prev = rd_ctrl; ctrl_prev = rd_ctrl;
@ -184,8 +184,8 @@ static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int
lo |= bytes[i] << (8*i); lo |= bytes[i] << (8*i);
for (; i < 8 && i < size; i++) for (; i < 8 && i < size; i++)
hi |= bytes[i] << (8*(i - 4)); hi |= bytes[i] << (8*(i - 4));
write32((unsigned long)&ehci_debug->data03, lo); write32(&ehci_debug->data03, lo);
write32((unsigned long)&ehci_debug->data47, hi); write32(&ehci_debug->data47, hi);
} }
static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size) static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
@ -194,8 +194,8 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
u32 lo, hi; u32 lo, hi;
int i; int i;
lo = read32((unsigned long)&ehci_debug->data03); lo = read32(&ehci_debug->data03);
hi = read32((unsigned long)&ehci_debug->data47); hi = read32(&ehci_debug->data47);
for (i = 0; i < 4 && i < size; i++) for (i = 0; i < 4 && i < size; i++)
bytes[i] = (lo >> (8*i)) & 0xff; bytes[i] = (lo >> (8*i)) & 0xff;
for (; i < 8 && i < size; i++) for (; i < 8 && i < size; i++)
@ -205,9 +205,9 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
#if CONFIG_DEBUG_USBDEBUG #if CONFIG_DEBUG_USBDEBUG
static void dbgp_print_data(struct ehci_dbg_port *ehci_debug) static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
{ {
u32 ctrl = read32((unsigned long)&ehci_debug->control); u32 ctrl = read32(&ehci_debug->control);
u32 lo = read32((unsigned long)&ehci_debug->data03); u32 lo = read32(&ehci_debug->data03);
u32 hi = read32((unsigned long)&ehci_debug->data47); u32 hi = read32(&ehci_debug->data47);
int len = DBGP_LEN(ctrl); int len = DBGP_LEN(ctrl);
if (len) { if (len) {
int i; int i;
@ -233,13 +233,13 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *p
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint); addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT); pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl |= DBGP_OUT; ctrl |= DBGP_OUT;
dbgp_set_data(ehci_debug, bytes, size); dbgp_set_data(ehci_debug, bytes, size);
write32((unsigned long)&ehci_debug->address, addr); write32(&ehci_debug->address, addr);
write32((unsigned long)&ehci_debug->pids, pids); write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout); ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
@ -264,12 +264,12 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint); addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_IN); pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl &= ~DBGP_OUT; ctrl &= ~DBGP_OUT;
write32((unsigned long)&ehci_debug->address, addr); write32(&ehci_debug->address, addr);
write32((unsigned long)&ehci_debug->pids, pids); write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout); ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret < 0) if (ret < 0)
return ret; return ret;
@ -324,14 +324,14 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint); addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP); pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req)); ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
ctrl |= DBGP_OUT; ctrl |= DBGP_OUT;
/* Setup stage */ /* Setup stage */
dbgp_set_data(ehci_debug, &req, sizeof(req)); dbgp_set_data(ehci_debug, &req, sizeof(req));
write32((unsigned long)&ehci_debug->address, addr); write32(&ehci_debug->address, addr);
write32((unsigned long)&ehci_debug->pids, pids); write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1); ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
if (ret < 0) if (ret < 0)
return ret; return ret;
@ -344,7 +344,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
/* Status stage in opposite direction */ /* Status stage in opposite direction */
pipe->pid = USB_PID_DATA1; pipe->pid = USB_PID_DATA1;
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, 0); ctrl = DBGP_LEN_UPDATE(ctrl, 0);
if (read) { if (read) {
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT); pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
@ -354,7 +354,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
ctrl &= ~DBGP_OUT; ctrl &= ~DBGP_OUT;
} }
write32((unsigned long)&ehci_debug->pids, pids); write32(&ehci_debug->pids, pids);
ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout); ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret2 < 0) if (ret2 < 0)
return ret2; return ret2;
@ -368,21 +368,21 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
int loop; int loop;
/* Reset the usb debug port */ /* Reset the usb debug port */
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); portsc = read32(&ehci_regs->port_status[port - 1]);
portsc &= ~PORT_PE; portsc &= ~PORT_PE;
portsc |= PORT_RESET; portsc |= PORT_RESET;
write32((unsigned long)&ehci_regs->port_status[port - 1], portsc); write32(&ehci_regs->port_status[port - 1], portsc);
dbgp_mdelay(HUB_ROOT_RESET_TIME); dbgp_mdelay(HUB_ROOT_RESET_TIME);
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); portsc = read32(&ehci_regs->port_status[port - 1]);
write32((unsigned long)&ehci_regs->port_status[port - 1], write32(&ehci_regs->port_status[port - 1],
portsc & ~(PORT_RWC_BITS | PORT_RESET)); portsc & ~(PORT_RWC_BITS | PORT_RESET));
loop = 100; loop = 100;
do { do {
dbgp_mdelay(1); dbgp_mdelay(1);
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); portsc = read32(&ehci_regs->port_status[port - 1]);
} while ((portsc & PORT_RESET) && (--loop > 0)); } while ((portsc & PORT_RESET) && (--loop > 0));
/* Device went away? */ /* Device went away? */
@ -407,7 +407,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
for (reps = 0; reps < 3; reps++) { for (reps = 0; reps < 3; reps++) {
dbgp_mdelay(100); dbgp_mdelay(100);
status = read32((unsigned long)&ehci_regs->status); status = read32(&ehci_regs->status);
if (status & STS_PCD) { if (status & STS_PCD) {
ret = ehci_reset_port(ehci_regs, port); ret = ehci_reset_port(ehci_regs, port);
if (ret == 0) if (ret == 0)
@ -440,7 +440,7 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
ehci_caps = (struct ehci_caps *)ehci_bar; ehci_caps = (struct ehci_caps *)ehci_bar;
ehci_regs = (struct ehci_regs *)(ehci_bar + ehci_regs = (struct ehci_regs *)(ehci_bar +
HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); HC_LENGTH(read32(&ehci_caps->hc_capbase)));
struct ehci_dbg_port *ehci_debug = info->ehci_debug; struct ehci_dbg_port *ehci_debug = info->ehci_debug;
@ -453,7 +453,7 @@ try_next_time:
port_map_tried = 0; port_map_tried = 0;
try_next_port: try_next_port:
hcs_params = read32((unsigned long)&ehci_caps->hcs_params); hcs_params = read32(&ehci_caps->hcs_params);
debug_port = HCS_DEBUG_PORT(hcs_params); debug_port = HCS_DEBUG_PORT(hcs_params);
n_ports = HCS_N_PORTS(hcs_params); n_ports = HCS_N_PORTS(hcs_params);
@ -461,7 +461,7 @@ try_next_port:
dprintk(BIOS_INFO, "n_ports: %d\n", n_ports); dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
for (i = 1; i <= n_ports; i++) { for (i = 1; i <= n_ports; i++) {
portsc = read32((unsigned long)&ehci_regs->port_status[i-1]); portsc = read32(&ehci_regs->port_status[i-1]);
dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc); dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
} }
@ -474,15 +474,15 @@ try_next_port:
} }
/* Wait until the controller is halted */ /* Wait until the controller is halted */
status = read32((unsigned long)&ehci_regs->status); status = read32(&ehci_regs->status);
if (!(status & STS_HALT)) { if (!(status & STS_HALT)) {
cmd = read32((unsigned long)&ehci_regs->command); cmd = read32(&ehci_regs->command);
cmd &= ~CMD_RUN; cmd &= ~CMD_RUN;
write32((unsigned long)&ehci_regs->command, cmd); write32(&ehci_regs->command, cmd);
loop = 100; loop = 100;
do { do {
dbgp_mdelay(10); dbgp_mdelay(10);
status = read32((unsigned long)&ehci_regs->status); status = read32(&ehci_regs->status);
} while (!(status & STS_HALT) && (--loop > 0)); } while (!(status & STS_HALT) && (--loop > 0));
if (status & STS_HALT) if (status & STS_HALT)
dprintk(BIOS_INFO, "EHCI controller halted successfully.\n"); dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
@ -492,12 +492,12 @@ try_next_port:
loop = 100; loop = 100;
/* Reset the EHCI controller */ /* Reset the EHCI controller */
cmd = read32((unsigned long)&ehci_regs->command); cmd = read32(&ehci_regs->command);
cmd |= CMD_RESET; cmd |= CMD_RESET;
write32((unsigned long)&ehci_regs->command, cmd); write32(&ehci_regs->command, cmd);
do { do {
dbgp_mdelay(10); dbgp_mdelay(10);
cmd = read32((unsigned long)&ehci_regs->command); cmd = read32(&ehci_regs->command);
} while ((cmd & CMD_RESET) && (--loop > 0)); } while ((cmd & CMD_RESET) && (--loop > 0));
if(!loop) { if(!loop) {
@ -509,25 +509,25 @@ try_next_port:
} }
/* Claim ownership, but do not enable yet */ /* Claim ownership, but do not enable yet */
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_OWNER; ctrl |= DBGP_OWNER;
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE); ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
write32((unsigned long)&ehci_debug->control, ctrl); write32(&ehci_debug->control, ctrl);
/* Start EHCI controller */ /* Start EHCI controller */
cmd = read32((unsigned long)&ehci_regs->command); cmd = read32(&ehci_regs->command);
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET); cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
cmd |= CMD_RUN; cmd |= CMD_RUN;
write32((unsigned long)&ehci_regs->command, cmd); write32(&ehci_regs->command, cmd);
/* Ensure everything is routed to the EHCI */ /* Ensure everything is routed to the EHCI */
write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF); write32(&ehci_regs->configured_flag, FLAG_CF);
/* Wait until the controller is no longer halted */ /* Wait until the controller is no longer halted */
loop = 10; loop = 10;
do { do {
dbgp_mdelay(10); dbgp_mdelay(10);
status = read32((unsigned long)&ehci_regs->status); status = read32(&ehci_regs->status);
} while ((status & STS_HALT) && (--loop > 0)); } while ((status & STS_HALT) && (--loop > 0));
if(!loop) { if(!loop) {
@ -546,13 +546,13 @@ try_next_port:
/* Enable the debug port */ /* Enable the debug port */
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_CLAIM; ctrl |= DBGP_CLAIM;
write32((unsigned long)&ehci_debug->control, ctrl); write32(&ehci_debug->control, ctrl);
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) { if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
dprintk(BIOS_INFO, "No device in EHCI debug port.\n"); dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM); write32(&ehci_debug->control, ctrl & ~DBGP_CLAIM);
ret = -4; ret = -4;
goto err; goto err;
} }
@ -560,9 +560,9 @@ try_next_port:
#if 0 #if 0
/* Completely transfer the debug device to the debug controller */ /* Completely transfer the debug device to the debug controller */
portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]); portsc = read32(&ehci_regs->port_status[debug_port - 1]);
portsc &= ~PORT_PE; portsc &= ~PORT_PE;
write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc); write32(&ehci_regs->port_status[debug_port - 1], portsc);
#endif #endif
dbgp_mdelay(100); dbgp_mdelay(100);
@ -577,9 +577,9 @@ try_next_port:
return 0; return 0;
err: err:
/* Things didn't work so remove my claim */ /* Things didn't work so remove my claim */
ctrl = read32((unsigned long)&ehci_debug->control); ctrl = read32(&ehci_debug->control);
ctrl &= ~(DBGP_CLAIM | DBGP_OUT); ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl); write32(&ehci_debug->control, ctrl);
//return ret; //return ret;
next_debug_port: next_debug_port:

6
src/drivers/usb/pci_ehci.c
View File

@ -103,13 +103,13 @@ void pci_ehci_read_resources(struct device *dev)
} }
#endif #endif
unsigned long pci_ehci_base_regs(pci_devfn_t sdev) u8 *pci_ehci_base_regs(pci_devfn_t sdev)
{ {
#ifdef __SIMPLE_DEVICE__ #ifdef __SIMPLE_DEVICE__
unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
#else #else
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev)); device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f; u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
#endif #endif
return base + HC_LENGTH(read32(base)); return base + HC_LENGTH(read32(base));
} }

2
src/include/device/pci_ehci.h
View File

@ -28,7 +28,7 @@
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ #define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx); pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
unsigned long pci_ehci_base_regs(pci_devfn_t dev); u8 *pci_ehci_base_regs(pci_devfn_t dev);
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base); void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);

6
src/include/device/resource.h
View File

@ -74,4 +74,10 @@ extern void search_global_resources(
#define RESOURCE_TYPE_MAX 20 #define RESOURCE_TYPE_MAX 20
extern const char *resource_type(struct resource *resource); extern const char *resource_type(struct resource *resource);
static inline void *res2mmio(struct resource *res, unsigned long offset,
unsigned long mask)
{
return (void *)(uintptr_t)((res->base + offset) & ~mask);
}
#endif /* DEVICE_RESOURCE_H */ #endif /* DEVICE_RESOURCE_H */

12
src/lib/reg_script.c
View File

@ -155,11 +155,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
switch (step->size) { switch (step->size) {
case REG_SCRIPT_SIZE_8: case REG_SCRIPT_SIZE_8:
return read8(step->reg); return read8((u8 *)step->reg);
case REG_SCRIPT_SIZE_16: case REG_SCRIPT_SIZE_16:
return read16(step->reg); return read16((u16 *)step->reg);
case REG_SCRIPT_SIZE_32: case REG_SCRIPT_SIZE_32:
return read32(step->reg); return read32((u32 *)step->reg);
} }
return 0; return 0;
} }
@ -170,13 +170,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx)
switch (step->size) { switch (step->size) {
case REG_SCRIPT_SIZE_8: case REG_SCRIPT_SIZE_8:
write8(step->reg, step->value); write8((u8 *)step->reg, step->value);
break; break;
case REG_SCRIPT_SIZE_16: case REG_SCRIPT_SIZE_16:
write16(step->reg, step->value); write16((u16 *)step->reg, step->value);
break; break;
case REG_SCRIPT_SIZE_32: case REG_SCRIPT_SIZE_32:
write32(step->reg, step->value); write32((u32 *)step->reg, step->value);
break; break;
} }
} }

2
src/mainboard/advansus/a785e-i/mptable.c
View File

@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0; dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword); smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) { for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00); outb(byte | 0x80, 0xC00);

2
src/mainboard/amd/bimini_fam10/mptable.c
View File

@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
dword |= (pm_ioread(0x35) & 0xFF) << 8; dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16; dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24; dword |= (pm_ioread(0x37) & 0xFF) << 24;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword); smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) { for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00); outb(byte | 0x80, 0xC00);

3
src/mainboard/amd/dbm690t/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0)); PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb600, 0x11, dword); smp_write_ioapic(mc, apicid_sb600,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

6
src/mainboard/amd/dinar/mptable.c
View File

@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sb700; u32 apicid_sb700;
u32 apicid_rd890; u32 apicid_rd890;
device_t dev; device_t dev;
u32 dword; u8 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR); mptable_init(mc, LOCAL_APIC_ADDR);
@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) { if (dev) {
/* Set sb700 IOAPIC ID */ /* Set sb700 IOAPIC ID */
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = (u8 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sb700, 0x20, dword); smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
/* /*
@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) { if (dev) {
pci_write_config32(dev, 0xF8, 0x1); pci_write_config32(dev, 0xF8, 0x1);
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; dword = (u8 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_rd890, 0x20, dword); smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
} }

6
src/mainboard/amd/inagua/mptable.c
View File

@ -52,8 +52,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte; u8 byte;

3
src/mainboard/amd/mahogany/mptable.c
View File

@ -60,7 +60,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

3
src/mainboard/amd/mahogany_fam10/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

8
src/mainboard/amd/olivehill/mptable.c
View File

@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00); outb(byte, 0xC00);

8
src/mainboard/amd/olivehillplus/mptable.c
View File

@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00); outb(byte, 0xC00);

6
src/mainboard/amd/parmer/mptable.c
View File

@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {

6
src/mainboard/amd/persimmon/mptable.c
View File

@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */ /* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs: * Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address * APIC ID, Version, APIC Flags:EN, Address
*/ */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* /*
* Type 3: I/O Interrupt Table Entries: * Type 3: I/O Interrupt Table Entries:

3
src/mainboard/amd/pistachio/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0)); PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb600, 0x11, dword); smp_write_ioapic(mc, apicid_sb600,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

14
src/mainboard/amd/serengeti_cheetah/mptable.c
View File

@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
res2mmio(res, 0, 0));
} }
} }
@ -60,14 +62,16 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
res2mmio(res, 0, 0));
} }
} }
break; break;

14
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
@ -56,14 +56,16 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
res2mmio(res, 0, 0));
} }
} }
@ -79,14 +81,16 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
res2mmio(res, 0, 0));
} }
} }
break; break;

6
src/mainboard/amd/south_station/mptable.c
View File

@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte; u8 byte;

6
src/mainboard/amd/thatcher/mptable.c
View File

@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {

3
src/mainboard/amd/tilapia_fam10/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

4
src/mainboard/amd/torpedo/mptable.c
View File

@ -107,11 +107,11 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
u32 dword; u8 *dword;
u8 byte; u8 byte;
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0; dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
/* Set IO APIC ID onto IO_APIC_ID */ /* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00); write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24); write32 (dword + 0x10, IO_APIC_ID << 24);

6
src/mainboard/amd/union_station/mptable.c
View File

@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte; u8 byte;

2
src/mainboard/apple/macbook21/mptable.c
View File

@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus); mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */ /* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);

8
src/mainboard/arima/hdama/mptable.c
View File

@ -125,7 +125,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */ /* IOAPIC handling */
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
@ -134,7 +134,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_1, 0x11,
res2mmio(res, 0, 0));
} }
} }
/* 8131 apic 4 */ /* 8131 apic 4 */
@ -142,7 +143,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_2, 0x11,
res2mmio(res, 0, 0));
} }
} }
} }

3
src/mainboard/asrock/939a785gmh/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

6
src/mainboard/asrock/e350m1/mptable.c
View File

@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte; u8 byte;

8
src/mainboard/asrock/imb-a180/mptable.c
View File

@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -93,9 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00); outb(byte, 0xC00);

2
src/mainboard/asus/a8n_e/mptable.c
View File

@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, smp_write_ioapic(mc, apicid_ck804, 0x11,
res->base); res2mmio(res, 0, 0));
} }
/* Initialize interrupt mapping. */ /* Initialize interrupt mapping. */

4
src/mainboard/asus/a8v-e_deluxe/mptable.c
View File

@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);

4
src/mainboard/asus/a8v-e_se/mptable.c
View File

@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);

4
src/mainboard/asus/dsbf/devicetree.cb
View File

@ -91,13 +91,13 @@ chip northbridge/intel/i5000
register "have_isa_interrupts" = "1" register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1" register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1" register "enable_virtual_wire" = "1"
register "base" = "0xfec00000" register "base" = "(void *)0xfec00000"
device ioapic 8 on end device ioapic 8 on end
end end
chip drivers/generic/ioapic chip drivers/generic/ioapic
register "irq_on_fsb" = "1" register "irq_on_fsb" = "1"
register "base" = "0xfec80000" register "base" = "(void *)0xfec80000"
device ioapic 9 on end device ioapic 9 on end
end end

4
src/mainboard/asus/dsbf/romstage.c
View File

@ -49,7 +49,7 @@ static void early_config(void)
u32 gcs, rpc, fd; u32 gcs, rpc, fd;
/* Enable RCBA */ /* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Disable watchdog */ /* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS); gcs = read32(DEFAULT_RCBA + RCBA_GCS);
@ -138,7 +138,7 @@ void main(unsigned long bist)
smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x08, 0x06);
smbus_write_byte(0x6f, 0x09, 0x00); smbus_write_byte(0x6f, 0x09, 0x00);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
i5000_fbdimm_init(); i5000_fbdimm_init();
smbus_write_byte(0x69, 0x01, 0x01); smbus_write_byte(0x69, 0x01, 0x01);
} }

6
src/mainboard/asus/f2a85-m/mptable.c
View File

@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {

4
src/mainboard/asus/k8v-x/mptable.c
View File

@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);

3
src/mainboard/asus/kfsn4-dre/mptable.c
View File

@ -62,7 +62,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); smp_write_ioapic(mc, apicid_ck804, 0x11,
res2mmio(res, 0, 0));
} }
/* Initialize interrupt mapping. */ /* Initialize interrupt mapping. */

3
src/mainboard/asus/m2n-e/mptable.c
View File

@ -56,7 +56,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) if (res)
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); smp_write_ioapic(mc, apicid_mcp55, 0x11,
res2mmio(res, 0, 0));
pci_write_config32(dev, 0x7c, 0x00000000); pci_write_config32(dev, 0x7c, 0x00000000);
pci_write_config32(dev, 0x80, 0x11002009); pci_write_config32(dev, 0x80, 0x11002009);

4
src/mainboard/asus/m2v/mptable.c
View File

@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR); smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, VIO_APIC_VADDR);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE); smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, (void*)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);

3
src/mainboard/asus/m4a78-em/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

3
src/mainboard/asus/m4a785-m/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

2
src/mainboard/asus/m5a88-v/mptable.c
View File

@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0; dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword); smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) { for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00); outb(byte | 0x80, 0xC00);

2
src/mainboard/asus/p2b-d/mptable.c
View File

@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
ioapic_id = 2; ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* Legacy Interrupts */ /* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);

2
src/mainboard/asus/p2b-ds/mptable.c
View File

@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
ioapic_id = 2; ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* Legacy Interrupts */ /* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);

2
src/mainboard/avalue/eax-785e/mptable.c
View File

@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0; dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword); smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) { for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00); outb(byte | 0x80, 0xC00);

4
src/mainboard/broadcom/blast/mptable.c
View File

@ -41,7 +41,9 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base); smp_write_ioapic(mc, apicid_bcm5785[i],
0x11,
res2mmio(res, 0, 0));
} }
} }
} }

2
src/mainboard/getac/p470/mptable.c
View File

@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus); mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */ /* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);

3
src/mainboard/gigabyte/ga_2761gxdk/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_sis966, 0x11, res->base); smp_write_ioapic(mc, apicid_sis966, 0x11,
res2mmio(res, 0, 0));
} }
dword = 0x43c6c643; dword = 0x43c6c643;

3
src/mainboard/gigabyte/m57sli/mptable.c
View File

@ -57,7 +57,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); smp_write_ioapic(mc, apicid_mcp55, 0x11,
res2mmio(res, 0, 0));
} }
/* set up the interrupt registers of mcp55 */ /* set up the interrupt registers of mcp55 */
pci_write_config32(dev, 0x7c, 0xc643c643); pci_write_config32(dev, 0x7c, 0xc643c643);

3
src/mainboard/gigabyte/ma785gm/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

3
src/mainboard/gigabyte/ma785gmt/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

3
src/mainboard/gigabyte/ma78gm/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

6
src/mainboard/gizmosphere/gizmo/mptable.c
View File

@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte; u8 byte;

6
src/mainboard/gizmosphere/gizmo2/mptable.c
View File

@ -40,8 +40,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */ /* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs: * Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address * APIC ID, Version, APIC Flags:EN, Address
*/ */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* /*
* Type 3: I/O Interrupt Table Entries: * Type 3: I/O Interrupt Table Entries:

6
src/mainboard/google/bolt/romstage.c
View File

@ -102,15 +102,15 @@ void mainboard_romstage_entry(unsigned long bist)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR, .pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = DEFAULT_RCBA, .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,

6
src/mainboard/google/butterfly/romstage.c
View File

@ -81,15 +81,15 @@ void main(unsigned long bist)
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS, .hpet_address = CONFIG_HPET_ADDRESS,
.rcba = DEFAULT_RCBABASE, .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000, .thermalbase = 0xfed08000,

6
src/mainboard/google/falco/romstage.c
View File

@ -111,15 +111,15 @@ void mainboard_romstage_entry(unsigned long bist)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR, .pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = DEFAULT_RCBA, .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,

6
src/mainboard/google/link/romstage.c
View File

@ -122,15 +122,15 @@ void main(unsigned long bist)
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS, .hpet_address = CONFIG_HPET_ADDRESS,
.rcba = DEFAULT_RCBABASE, .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000, .thermalbase = 0xfed08000,

6
src/mainboard/google/panther/romstage.c
View File

@ -81,15 +81,15 @@ void mainboard_romstage_entry(unsigned long bist)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR, .pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = DEFAULT_RCBA, .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,

6
src/mainboard/google/parrot/romstage.c
View File

@ -81,15 +81,15 @@ void main(unsigned long bist)
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS, .hpet_address = CONFIG_HPET_ADDRESS,
.rcba = DEFAULT_RCBABASE, .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000, .thermalbase = 0xfed08000,

6
src/mainboard/google/peppy/romstage.c
View File

@ -122,15 +122,15 @@ void mainboard_romstage_entry(unsigned long bist)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR, .pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = DEFAULT_RCBA, .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,

6
src/mainboard/google/slippy/romstage.c
View File

@ -137,15 +137,15 @@ void mainboard_romstage_entry(unsigned long bist)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR, .pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = DEFAULT_RCBA, .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,

6
src/mainboard/google/stout/romstage.c
View File

@ -122,15 +122,15 @@ void main(unsigned long bist)
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS, .hpet_address = CONFIG_HPET_ADDRESS,
.rcba = DEFAULT_RCBABASE, .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000, .thermalbase = 0xfed08000,

8
src/mainboard/hp/abm/mptable.c
View File

@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -93,9 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00); outb(byte, 0xC00);

8
src/mainboard/hp/dl145_g1/mptable.c
View File

@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR);
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base); smp_write_ioapic(mc, m->apicid_8131_1, 0x20,
res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base); smp_write_ioapic(mc, m->apicid_8131_2, 0x20,
res2mmio(res, 0, 0));
} }
} }

3
src/mainboard/hp/dl145_g3/mptable.c
View File

@ -67,7 +67,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base); printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
res2mmio(res, 0, 0));
} }
} }
} }

3
src/mainboard/hp/dl165_g6_fam10/mptable.c
View File

@ -68,7 +68,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base); printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base);
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
res2mmio(res, 0, 0));
} }
} }
} }

6
src/mainboard/hp/pavilion_m6_1035dx/mptable.c
View File

@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct * have been written so they can be read to get the correct
* APIC ID and Version * APIC ID and Version
*/ */
u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA "); my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {

2
src/mainboard/ibase/mb899/mptable.c
View File

@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
ioapic_id = 2; ioapic_id = 2;
smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, ioapic_id, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */ /* Legacy Interrupts */

8
src/mainboard/ibm/e325/mptable.c
View File

@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */ /* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
@ -67,7 +67,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base); smp_write_ioapic(mc, 0x03, 0x11,
res2mmio(res, 0, 0));
} }
} }
/* 8131-2 apic #4 */ /* 8131-2 apic #4 */
@ -75,7 +76,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base); smp_write_ioapic(mc, 0x04, 0x11,
res2mmio(res, 0, 0));
} }
} }
} }

8
src/mainboard/ibm/e326/mptable.c
View File

@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */ /* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
@ -66,7 +66,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base); smp_write_ioapic(mc, 0x03, 0x11,
res2mmio(res, 0, 0));
} }
} }
/* 8131-2 apic #4 */ /* 8131-2 apic #4 */
@ -74,7 +75,8 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base); smp_write_ioapic(mc, 0x04, 0x11,
res2mmio(res, 0, 0));
} }
} }
} }

3
src/mainboard/iei/kino-780am2-fam10/mptable.c
View File

@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0)); PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) { if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0; dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword); smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */ /* Initialize interrupt mapping */
/* aza */ /* aza */

6
src/mainboard/intel/baskingridge/romstage.c
View File

@ -71,15 +71,15 @@ void mainboard_romstage_entry(unsigned long bist)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR, .pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = DEFAULT_RCBA, .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,

2
src/mainboard/intel/d945gclf/mptable.c
View File

@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus); mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */ /* Legacy Interrupts */

6
src/mainboard/intel/eagleheights/mptable.c
View File

@ -67,14 +67,14 @@ static void *smp_write_config_table(void *v)
uint32_t pin, route; uint32_t pin, route;
device_t dev; device_t dev;
struct resource *res; struct resource *res;
unsigned long rcba; u8 *rcba;
dev = dev_find_slot(0, PCI_DEVFN(0x1F,0)); dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
res = find_resource(dev, RCBA); res = find_resource(dev, RCBA);
if (!res) { if (!res) {
return NULL; return NULL;
} }
rcba = res->base; rcba = res2mmio(res, 0, 0);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -121,7 +121,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);

2
src/mainboard/intel/eagleheights/romstage.c
View File

@ -83,7 +83,7 @@ static void early_config(void)
u32 gcs, rpc, fd; u32 gcs, rpc, fd;
/* Enable RCBA */ /* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Disable watchdog */ /* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS); gcs = read32(DEFAULT_RCBA + RCBA_GCS);

6
src/mainboard/intel/emeraldlake2/romstage.c
View File

@ -135,15 +135,15 @@ void main(unsigned long bist)
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000, .wdbbar = 0x4000000,
.wdbsize = 0x1000, .wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS, .hpet_address = CONFIG_HPET_ADDRESS,
.rcba = DEFAULT_RCBABASE, .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000, .thermalbase = 0xfed08000,

2
src/mainboard/intel/mohonpeak/romstage.c
View File

@ -32,7 +32,7 @@
static void interrupt_routing_config(void) static void interrupt_routing_config(void)
{ {
u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf; u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf);
/* /*
* Initialize Interrupt Routings for each device in ilb_base_address. * Initialize Interrupt Routings for each device in ilb_base_address.

2
src/mainboard/intel/mtarvon/mptable.c
View File

@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */ /* IOAPIC handling */
smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0); mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);

2
src/mainboard/intel/truxton/mptable.c
View File

@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */ /* IOAPIC handling */
smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0); mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);

2
src/mainboard/iwave/iWRainbowG6/mptable.c
View File

@ -34,7 +34,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc); smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus); mptable_write_buses(mc, NULL, &isa_bus);
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;

14
src/mainboard/iwill/dk8_htx/mptable.c
View File

@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
res2mmio(res, 0, 0));
} }
} }
@ -60,14 +62,16 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
res2mmio(res, 0, 0));
} }
} }
break; break;

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