Trivial changes to i82830 raminit.c for USE_PRINTK_IN_CAR.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
Joseph Smith
parent
948f922342
commit
bdf26a6bf5
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@ -30,16 +30,10 @@ Macros and definitions.
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/* Debugging macros. */
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#if CONFIG_DEBUG_RAM_SETUP
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#define PRINT_DEBUG(x) print_debug(x)
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#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
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#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
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#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
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#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
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#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
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#else
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#define PRINT_DEBUG(x)
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#define PRINT_DEBUG_HEX8(x)
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#define PRINT_DEBUG_HEX16(x)
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#define PRINT_DEBUG_HEX32(x)
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#define PRINTK_DEBUG(x...)
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#define DUMPNORTH()
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#endif
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@ -75,37 +69,19 @@ static void do_ram_command(u32 command)
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/* Clear bits 29, 10-8, 6-4. */
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reg32 &= 0xdffff88f;
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reg32 |= command << 4;
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PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32);
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pci_write_config32(NORTHBRIDGE, DRC, reg32);
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PRINT_DEBUG("RAM command 0x");
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PRINT_DEBUG_HEX32(reg32);
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PRINT_DEBUG("\n");
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}
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static void ram_read32(u8 dimm_start, u32 offset)
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{
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if (offset == 0x55aa55aa) {
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PRINT_DEBUG(" Reading RAM at 0x");
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PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
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PRINT_DEBUG(" => 0x");
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PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
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PRINT_DEBUG("\n");
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PRINT_DEBUG(" Writing RAM at 0x");
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PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
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PRINT_DEBUG(" <= 0x");
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PRINT_DEBUG_HEX32(offset);
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PRINT_DEBUG("\n");
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PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024));
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PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", (dimm_start * 32 * 1024 * 1024), offset);
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write32(dimm_start * 32 * 1024 * 1024, offset);
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PRINT_DEBUG(" Reading RAM at 0x");
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PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
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PRINT_DEBUG(" => 0x");
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PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
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PRINT_DEBUG("\n");
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PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024));
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} else {
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PRINT_DEBUG(" Sending RAM command to 0x");
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PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset);
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PRINT_DEBUG("\n");
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PRINTK_DEBUG(" to 0x%08x\n", (dimm_start * 32 * 1024 * 1024) + offset);
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read32((dimm_start * 32 * 1024 * 1024) + offset);
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}
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}
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@ -138,24 +114,22 @@ static void initialize_dimm_rows(void)
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dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row);
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if (dimm_end > dimm_start) {
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print_debug("Initializing SDRAM Row ");
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print_debug_hex8(row);
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print_debug("\n");
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printk(BIOS_DEBUG, "Initializing SDRAM Row %u\n", row);
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/* NOP command */
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PRINT_DEBUG(" NOP ");
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PRINTK_DEBUG(" NOP\n");
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do_ram_command(RAM_COMMAND_NOP);
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ram_read32(dimm_start, 0);
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udelay(200);
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/* Pre-charge all banks (at least 200 us after NOP) */
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PRINT_DEBUG(" Pre-charging all banks ");
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PRINTK_DEBUG(" Pre-charging all banks\n");
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do_ram_command(RAM_COMMAND_PRECHARGE);
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ram_read32(dimm_start, 0);
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udelay(1);
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/* 8 CBR refreshes (Auto Refresh) */
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PRINT_DEBUG(" 8 CBR refreshes ");
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PRINTK_DEBUG(" 8 CBR refreshes\n");
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for (i = 0; i < 8; i++) {
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do_ram_command(RAM_COMMAND_CBR);
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ram_read32(dimm_start, 0);
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@ -164,19 +138,19 @@ static void initialize_dimm_rows(void)
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/* MRS command */
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/* TODO: Set offset 0x1d0 according to DRT values */
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PRINT_DEBUG(" MRS ");
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PRINTK_DEBUG(" MRS\n");
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do_ram_command(RAM_COMMAND_MRS);
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ram_read32(dimm_start, 0x1d0);
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udelay(2);
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/* Set GMCH-M Mode Select bits back to NORMAL operation mode */
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PRINT_DEBUG(" Normal operation mode ");
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PRINTK_DEBUG(" Normal operation mode\n");
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do_ram_command(RAM_COMMAND_NORMAL);
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ram_read32(dimm_start, 0);
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udelay(1);
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/* Perform a dummy memory read/write cycle */
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PRINT_DEBUG(" Performing dummy read/write\n");
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PRINTK_DEBUG(" Performing dummy read/write\n");
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ram_read32(dimm_start, 0x55aa55aa);
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udelay(1);
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}
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@ -253,30 +227,22 @@ static void set_dram_row_boundaries(void)
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/* First check if a DIMM is actually present. */
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if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
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print_debug("Found DIMM in slot ");
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print_debug_hex8(i);
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print_debug("\n");
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printk(BIOS_DEBUG, "Found DIMM in slot %u\n", i);
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sz = spd_get_dimm_size(device);
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/* WISHLIST: would be nice to display it as decimal? */
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print_debug("DIMM is 0x");
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print_debug_hex16(sz.side1);
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print_debug(" on side 1\n");
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print_debug("DIMM is 0x");
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print_debug_hex16(sz.side2);
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print_debug(" on side 2\n");
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printk(BIOS_DEBUG, " DIMM is %uMB on side 1\n", sz.side1);
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printk(BIOS_DEBUG, " DIMM is %uMB on side 2\n", sz.side2);
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/* - Memory compatibility checks - */
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/* Test for PC133 (i82830 only supports PC133) */
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/* PC133 SPD9 - cycle time is always 75 */
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if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
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print_err("SPD9 DIMM Is Not PC133 Compatable\n");
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printk(BIOS_ERR, "SPD9 DIMM Is Not PC133 Compatable\n");
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die("HALT\n");
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}
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/* PC133 SPD10 - access time is always 54 */
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if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
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print_err("SPD10 DIMM Is Not PC133 Compatable\n");
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printk(BIOS_ERR, "SPD10 DIMM Is Not PC133 Compatable\n");
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die("HALT\n");
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}
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@ -285,22 +251,20 @@ static void set_dram_row_boundaries(void)
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* side or larger than 256MB per side.
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*/
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if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
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print_err("This northbridge only supports\n");
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print_err("symmetrical dual-sided DIMMs\n");
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print_err("booting as a single-sided DIMM\n");
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printk(BIOS_ERR, "This northbridge only supports\n");
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printk(BIOS_ERR, "symmetrical dual-sided DIMMs\n");
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printk(BIOS_ERR, "booting as a single-sided DIMM\n");
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sz.side2 = 0;
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}
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if ((sz.side1 < 32)) {
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print_err("DIMMs smaller than 32MB per side\n");
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print_err("are not supported on this northbridge\n");
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printk(BIOS_ERR, "DIMMs smaller than 32MB per side\n");
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printk(BIOS_ERR, "are not supported on this northbridge\n");
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die("HALT\n");
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}
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if ((sz.side1 > 256)) {
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print_err
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("DIMMs larger than 256MB per side\n");
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print_err
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("are not supported on this northbridge\n");
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printk(BIOS_ERR, "DIMMs larger than 256MB per side\n");
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printk(BIOS_ERR, "are not supported on this northbridge\n");
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die("HALT\n");
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}
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/* - End Memory compatibility checks - */
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@ -313,9 +277,7 @@ static void set_dram_row_boundaries(void)
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if (sz.side2)
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drb2 = sz.side2 / 32;
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} else {
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PRINT_DEBUG("No DIMM found in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\n");
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printk(BIOS_DEBUG, "No DIMM found in slot %u\n", i);
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/* If there's no DIMM in the slot, set value to 0. */
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drb1 = 0;
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@ -325,30 +287,14 @@ static void set_dram_row_boundaries(void)
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if (i == 0) {
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pci_write_config8(NORTHBRIDGE, DRB, drb1);
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pci_write_config8(NORTHBRIDGE, DRB + 1, drb1 + drb2);
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PRINT_DEBUG("DRB 0x");
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PRINT_DEBUG_HEX8(DRB);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(drb1);
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PRINT_DEBUG("\n");
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PRINT_DEBUG("DRB1 0x");
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PRINT_DEBUG_HEX8(DRB + 1);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(drb1 + drb2);
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PRINT_DEBUG("\n");
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PRINTK_DEBUG(" DRB 0x%02x has been set to 0x%02x\n", DRB, drb1);
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PRINTK_DEBUG(" DRB1 0x%02x has been set to 0x%02x\n", DRB + 1, drb1 + drb2);
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} else if (i == 1) {
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value = pci_read_config8(NORTHBRIDGE, DRB + 1);
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pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
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pci_write_config8(NORTHBRIDGE, DRB + 3, value + drb1 + drb2);
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PRINT_DEBUG("DRB2 0x");
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PRINT_DEBUG_HEX8(DRB + 2);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(value + drb1);
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PRINT_DEBUG("\n");
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PRINT_DEBUG("DRB3 0x");
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PRINT_DEBUG_HEX8(DRB + 3);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(value + drb1 + drb2);
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PRINT_DEBUG("\n");
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PRINTK_DEBUG(" DRB2 0x%02x has been set to 0x%02x\n", DRB + 2, value + drb1);
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PRINTK_DEBUG(" DRB3 0x%02x has been set to 0x%02x\n", DRB + 3, value + drb1 + drb2);
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/* We need to set the highest DRB value to 0x64 and 0x65.
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* These are supposed to be "Reserved" but memory will
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@ -371,9 +317,7 @@ static void set_dram_row_attributes(void)
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/* First check if a DIMM is actually present. */
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if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
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print_debug("Found DIMM in slot ");
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print_debug_hex8(i);
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print_debug(", setting DRA...\n");
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PRINTK_DEBUG("Found DIMM in slot %u\n", i);
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dra = 0x00;
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@ -402,7 +346,7 @@ static void set_dram_row_attributes(void)
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} else if (dra == 16) {
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dra = 0xF3; /* 16KB */
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} else {
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print_err("Page size not supported\n");
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printk(BIOS_ERR, "Page size not supported\n");
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die("HALT\n");
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}
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} else if (value == 2) {
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@ -415,18 +359,16 @@ static void set_dram_row_attributes(void)
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} else if (dra == 16) {
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dra = 0x33; /* 16KB */
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} else {
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print_err("Page size not supported\n");
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printk(BIOS_ERR, "Page size not supported\n");
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die("HALT\n");
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}
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} else {
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print_err("# of banks of DIMM not supported\n");
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printk(BIOS_ERR, "# of banks of DIMM not supported\n");
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die("HALT\n");
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}
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} else {
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PRINT_DEBUG("No DIMM found in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG(", setting DRA to 0xFF\n");
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PRINTK_DEBUG("No DIMM found in slot %u\n", i);
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/* If there's no DIMM in the slot, set dra value to 0xFF. */
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dra = 0xFF;
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@ -434,11 +376,7 @@ static void set_dram_row_attributes(void)
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/* Set the value for DRAM Row Attribute Registers */
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pci_write_config8(NORTHBRIDGE, DRA + i, dra);
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PRINT_DEBUG("DRA 0x");
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PRINT_DEBUG_HEX8(DRA + i);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(dra);
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PRINT_DEBUG("\n");
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PRINTK_DEBUG(" DRA 0x%02x has been set to 0x%02x\n", DRA + i, dra);
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}
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}
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@ -467,7 +405,7 @@ Public interface.
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static void sdram_set_registers(void)
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{
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PRINT_DEBUG("Setting initial sdram registers....\n");
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PRINTK_DEBUG("Setting initial sdram registers....\n");
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/* Calculate the value for DRT DRAM Timing Register */
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set_dram_timing();
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@ -481,7 +419,7 @@ static void sdram_set_registers(void)
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/* Setup DRAM Row Attribute Registers */
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set_dram_row_attributes();
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PRINT_DEBUG("Initial sdram registers have been set.\n");
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PRINTK_DEBUG("Initial sdram registers have been set.\n");
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}
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static void northbridge_set_registers(void)
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@ -489,7 +427,7 @@ static void northbridge_set_registers(void)
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u16 value;
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int igd_memory = 0;
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PRINT_DEBUG("Setting initial nothbridge registers....\n");
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PRINTK_DEBUG("Setting initial nothbridge registers....\n");
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/* Set the value for Fixed DRAM Hole Control Register */
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pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
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@ -535,7 +473,7 @@ static void northbridge_set_registers(void)
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value |= 1; // 64MB aperture
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pci_write_config16(NORTHBRIDGE, GCC1, value);
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PRINT_DEBUG("Initial northbridge registers have been set.\n");
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PRINTK_DEBUG("Initial northbridge registers have been set.\n");
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}
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static void sdram_initialize(void)
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@ -545,20 +483,20 @@ static void sdram_initialize(void)
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/* Setup Initial SDRAM Registers */
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sdram_set_registers();
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/* 0. Wait until power/voltages and clocks are stable (200us). */
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/* Wait until power/voltages and clocks are stable (200us). */
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udelay(200);
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/* Initialize each row of memory one at a time */
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initialize_dimm_rows();
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/* Enable Refresh */
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PRINT_DEBUG("Enabling Refresh\n");
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PRINTK_DEBUG("Enabling Refresh\n");
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reg32 = pci_read_config32(NORTHBRIDGE, DRC);
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reg32 |= (RAM_COMMAND_REFRESH << 8);
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pci_write_config32(NORTHBRIDGE, DRC, reg32);
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/* Set initialization complete */
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PRINT_DEBUG("Setting initialization complete\n");
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PRINTK_DEBUG("Setting initialization complete\n");
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reg32 = pci_read_config32(NORTHBRIDGE, DRC);
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reg32 |= (RAM_COMMAND_IC << 29);
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pci_write_config32(NORTHBRIDGE, DRC, reg32);
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@ -566,6 +504,6 @@ static void sdram_initialize(void)
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/* Setup Initial Northbridge Registers */
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northbridge_set_registers();
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PRINT_DEBUG("Northbridge following SDRAM init:\n");
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PRINTK_DEBUG("Northbridge following SDRAM init:\n");
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DUMPNORTH();
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}
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