mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8 which is calibrated value for the board. BUG=b:207046230 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
parent
69ed3ed5d8
commit
be0722ac91
|
@ -2,6 +2,12 @@ chip soc/intel/jasperlake
|
||||||
# MIPI display panel
|
# MIPI display panel
|
||||||
register "DdiPortAConfig" = "2" # DdiPortMipiDsi
|
register "DdiPortAConfig" = "2" # DdiPortMipiDsi
|
||||||
|
|
||||||
|
# Enable Acoustic noise mitigation and set slew rate to 1/8
|
||||||
|
# Rest of the parameters are 0 by default.
|
||||||
|
register "AcousticNoiseMitigation" = "1"
|
||||||
|
register "SlowSlewRate" = "SlewRateFastBy8"
|
||||||
|
register "FastPkgCRampDisable" = "1"
|
||||||
|
|
||||||
# Disable PCIe Root Port 8 (index 7)
|
# Disable PCIe Root Port 8 (index 7)
|
||||||
register "PcieRpEnable[7]" = "0"
|
register "PcieRpEnable[7]" = "0"
|
||||||
# Disable PCIe Clock Source 4 (index 3)
|
# Disable PCIe Clock Source 4 (index 3)
|
||||||
|
|
Loading…
Reference in New Issue