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soc/intel/meteorlake: Expose In-Band ECC UPD config to mainboard 

Meteor Lake has a UPD config called In-Band ECC(IBECC) which uses a part of the system DRAM to store the ECC information. There are a few UPD parameters in FSP-M to configure this feature as needed.

This patch adds code to expose these parameters to the devicetree so
that they can be configured on the mainboard level as needed.

Change-Id: Ice1ede430d36dff4175a92941ee85cc933fa56d5
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Marx Wang 2023-10-19 15:15:22 +08:00 committed by Matt DeVillier
parent e68650a656
commit be0e694fcf
2 changed files with 42 additions and 0 deletions
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22
src/soc/intel/meteorlake/chip.h
View File

@ -18,9 +18,28 @@
#include <soc/usb.h> #include <soc/usb.h>
#include <stdint.h> #include <stdint.h>
/* Define config parameters for In-Band ECC (IBECC). */
#define MAX_IBECC_REGIONS 8
#define MAX_SAGV_POINTS 4 #define MAX_SAGV_POINTS 4
#define MAX_HD_AUDIO_SDI_LINKS 2 #define MAX_HD_AUDIO_SDI_LINKS 2
/* In-Band ECC Operation Mode */
enum ibecc_mode {
IBECC_MODE_PER_REGION,
IBECC_MODE_NONE,
IBECC_MODE_ALL
};
struct ibecc_config {
bool enable;
bool parity_en;
enum ibecc_mode mode;
bool region_enable[MAX_IBECC_REGIONS];
uint16_t region_base[MAX_IBECC_REGIONS];
uint16_t region_mask[MAX_IBECC_REGIONS];
};
/* Types of different SKUs */ /* Types of different SKUs */
enum soc_intel_meteorlake_power_limits { enum soc_intel_meteorlake_power_limits {
MTL_P_282_242_CORE, MTL_P_282_242_CORE,
@ -151,6 +170,9 @@ struct soc_intel_meteorlake_config {
/* TCC activation offset */ /* TCC activation offset */
uint32_t tcc_offset; uint32_t tcc_offset;
/* In-Band ECC (IBECC) configuration */
struct ibecc_config ibecc;
/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
* When enabled memory will be training at two different frequencies. * When enabled memory will be training at two different frequencies.
* 0:Disabled, 1:Enabled * 0:Disabled, 1:Enabled

20
src/soc/intel/meteorlake/romstage/fsp_params.c
View File

@ -361,6 +361,25 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
} }
} }
static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_meteorlake_config *config)
{
/* In-Band ECC configuration */
if (config->ibecc.enable) {
m_cfg->Ibecc = config->ibecc.enable;
m_cfg->IbeccParity = config->ibecc.parity_en;
m_cfg->IbeccOperationMode = config->ibecc.mode;
if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) {
FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionEnable,
config->ibecc.region_enable);
FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionBase,
config->ibecc.region_base);
FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionMask,
config->ibecc.region_mask);
}
}
}
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_meteorlake_config *config) const struct soc_intel_meteorlake_config *config)
{ {
@ -383,6 +402,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
fill_fspm_vtd_params, fill_fspm_vtd_params,
fill_fspm_trace_params, fill_fspm_trace_params,
fill_fspm_vr_config_params, fill_fspm_vr_config_params,
fill_fspm_ibecc_params,
}; };
for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)