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soc/amd/picasso: Use MSR_CSTATE_ADDRESS

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This is a standard MSR. No reason for picasso to define its own.

BUG=b:147042464
TEST=Boot to OS on trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2020-06-04 16:36:33 -06:00 committed by Patrick Georgi
parent f9b9166431
commit be2b5ac0ea
2 changed files with 2 additions and 3 deletions
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2
src/soc/amd/picasso/include/soc/cpu.h
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@ -3,8 +3,6 @@
#ifndef __PICASSO_CPU_H__ #ifndef __PICASSO_CPU_H__
#define __PICASSO_CPU_H__ #define __PICASSO_CPU_H__
#define CSTATE_BASE_REG 0xc0010073
int get_cpu_count(void); int get_cpu_count(void);
void check_mca(void); void check_mca(void);

3
src/soc/amd/picasso/southbridge.c
View file

@ -3,6 +3,7 @@
#include <console/console.h> #include <console/console.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <bootstate.h> #include <bootstate.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <device/device.h> #include <device/device.h>
@ -318,7 +319,7 @@ static void sb_init_acpi_ports(void)
/* CpuControl is in \_SB.CP00, 6 bytes */ /* CpuControl is in \_SB.CP00, 6 bytes */
cst_addr.hi = 0; cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL; cst_addr.lo = ACPI_CPU_CONTROL;
wrmsr(CSTATE_BASE_REG, cst_addr); wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(HAVE_SMI_HANDLER)) {
/* APMC - SMI Command Port */ /* APMC - SMI Command Port */