soc/intel/baytrail: add support for Intel GMA OpRegion

Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to generate ACPI OpRegion, save the
table address in ASLB, and restore table address upon S3 resume.

Implementation largely based on existing Broadwell code.

Test: boot Windows 10 on google/squawks with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.

Change-Id: Iab15e1de2bb7d8fbec2e8705a621cfca0f255d4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/soc/intel/baytrail/Kconfig

@@ -38,6 +38,8 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON
 	select HAVE_INTEL_FIRMWARE
 	select HAVE_SPI_CONSOLE_SUPPORT
+	select INTEL_GMA_ACPI
+	select INTEL_GMA_SWSMISCI
 
 config VBOOT
 	select VBOOT_STARTS_IN_ROMSTAGE

src/soc/intel/baytrail/acpi/globalnvs.asl

@@ -67,6 +67,48 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TOLM,	 32,	// 0x34 - Top of Low Memory
 	CBMC,	 32,	// 0x38 - coreboot mem console pointer
 
+	/* IGD OpRegion */
+	Offset (0xb4),
+	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
+	IBTT,	 8,	// 0xb8 - IGD boot panel device
+	IPAT,	 8,	// 0xb9 - IGD panel type cmos option
+	ITVF,	 8,	// 0xba - IGD TV format cmos option
+	ITVM,	 8,	// 0xbb - IGD TV minor format option
+	IPSC,	 8,	// 0xbc - IGD panel scaling
+	IBLC,	 8,	// 0xbd - IGD BLC config
+	IBIA,	 8,	// 0xbe - IGD BIA config
+	ISSC,	 8,	// 0xbf - IGD SSC config
+	I409,	 8,	// 0xc0 - IGD 0409 modified settings
+	I509,	 8,	// 0xc1 - IGD 0509 modified settings
+	I609,	 8,	// 0xc2 - IGD 0609 modified settings
+	I709,	 8,	// 0xc3 - IGD 0709 modified settings
+	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
+	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
+	IF1E,	 8,	// 0xc6 - IGD function 1 enable
+	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
+	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
+	NXD2,	32,	// 0xcc - IGD _DGS next DID2
+	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
+	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
+	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
+	NXD6,	32,	// 0xdc - IGD _DGS next DID6
+	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
+	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
+
+	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
+	PAVP,	 8,	// 0xe9 - IGD PAVP data
+	Offset (0xeb),
+	OSCC,	 8,	// 0xeb - PCIe OSC control
+	NPCE,	 8,	// 0xec - native pcie support
+	PLFL,	 8,	// 0xed - platform flavor
+	BREV,	 8,	// 0xee - board revision
+	DPBM,	 8,	// 0xef - digital port b mode
+	DPCM,	 8,	// 0xf0 - digital port c mode
+	DPDM,	 8,	// 0xf1 - digital port d mode
+	ALFP,	 8,	// 0xf2 - active lfp
+	IMON,	 8,	// 0xf3 - current graphics turbo imon value
+	MMIO,	 8,	// 0xf4 - 64bit mmio support
+
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>

src/soc/intel/baytrail/gfx.c

@@ -19,13 +19,16 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <drivers/intel/gma/opregion.h>
 #include <reg_script.h>
 #include <stdlib.h>
 
 #include <soc/gfx.h>
 #include <soc/iosf.h>
+#include <soc/nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <cbmem.h>
 
 #include "chip.h"
 
@@ -362,6 +365,19 @@ static void gfx_panel_setup(device_t dev)
 	}
 }
 
+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t *gnvs_ptr = gnvs;
+	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
+}
+
+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
+{
+	global_nvs_t *gnvs_ptr = gnvs;
+	if (gnvs_ptr)
+		gnvs_ptr->aslb = aslb;
+}
+
 static void gfx_init(device_t dev)
 {
 	/* Pre VBIOS Init */
@@ -377,6 +393,35 @@ static void gfx_init(device_t dev)
 
 	/* Post VBIOS Init */
 	gfx_post_vbios_init(dev);
+
+	/* Restore opregion on S3 resume */
+	intel_gma_restore_opregion();
+}
+
+static unsigned long
+gma_write_acpi_tables(struct device *const dev,
+		      unsigned long current,
+		      struct acpi_rsdp *const rsdp)
+{
+	igd_opregion_t *opregion = (igd_opregion_t *)current;
+	global_nvs_t *gnvs;
+
+	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
+		return current;
+
+	current += sizeof(igd_opregion_t);
+
+	/* GNVS has been already set up */
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+	if (gnvs) {
+		/* IGD OpRegion Base Address */
+		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
+	} else {
+		printk(BIOS_ERR, "Error: GNVS table not found.\n");
+	}
+
+	current = acpi_align_current(current);
+	return current;
 }
 
 static struct device_operations gfx_device_ops = {
@@ -385,6 +430,7 @@ static struct device_operations gfx_device_ops = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= gfx_init,
 	.ops_pci		= &soc_pci_ops,
+	.write_acpi_tables	= gma_write_acpi_tables,
 };
 
 static const struct pci_driver gfx_driver __pci_driver = {

src/soc/intel/baytrail/include/soc/nvs.h

@@ -59,7 +59,42 @@ typedef struct global_nvs_t {
 	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
 	u32	cbmc; /* 0x38 - coreboot memconsole */
-	u8	rsvd3[196];
+	u8	rsvd3[120]; /* 0x3c - 0xb3 - unused */
+
+	/* IGD OpRegion */
+	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
+	u8	ibtt; /* 0xb8 - IGD boot type */
+	u8	ipat; /* 0xb9 - IGD panel type */
+	u8	itvf; /* 0xba - IGD TV format */
+	u8	itvm; /* 0xbb - IGD TV minor format */
+	u8	ipsc; /* 0xbc - IGD Panel Scaling */
+	u8	iblc; /* 0xbd - IGD BLC configuration */
+	u8	ibia; /* 0xbe - IGD BIA configuration */
+	u8	issc; /* 0xbf - IGD SSC configuration */
+	u8	i409; /* 0xc0 - IGD 0409 modified settings */
+	u8	i509; /* 0xc1 - IGD 0509 modified settings */
+	u8	i609; /* 0xc2 - IGD 0609 modified settings */
+	u8	i709; /* 0xc3 - IGD 0709 modified settings */
+	u8	idmm; /* 0xc4 - IGD Power Conservation */
+	u8	idms; /* 0xc5 - IGD DVMT memory size */
+	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
+	u8	hvco; /* 0xc7 - IGD HPLL VCO */
+	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
+	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
+	u8	pavp; /* 0xe9 - IGD PAVP data */
+	u8	rsvd12; /* 0xea - rsvd */
+	u8	oscc; /* 0xeb - PCIe OSC control */
+	u8	npce; /* 0xec - native pcie support */
+	u8	plfl; /* 0xed - platform flavor */
+	u8	brev; /* 0xee - board revision */
+	u8	dpbm; /* 0xef - digital port b mode */
+	u8	dpcm; /* 0xf0 - digital port c mode */
+	u8	dpdm; /* 0xf1 - digital port c mode */
+	u8	alfp; /* 0xf2 - active lfp */
+	u8	imon; /* 0xf3 - current graphics turbo imon value */
+	u8	mmio; /* 0xf4 - 64bit mmio support */
+
+	u8	unused[11];
 
 	/* ChromeOS specific (0x100-0xfff)*/
 	chromeos_acpi_t chromeos;