mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI
Enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI on hatch, dedede, and volteer to use the common version of mainboard_get_dram_part_num(). Remove duplicate instances of mainboard_get_dram_part_num(). BUG=b:169789558, b:168724473 TEST="emerge-volteer coreboot && emerge-hatch coreboot && emerge-dedede coreboot" and verify it builds. Change-Id: I4e29d3e7ef0f3370eab9a6996a5c4a21a636b40e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45883 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -37,6 +37,7 @@ config CHROMEOS
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bool
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bool
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default y
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default y
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select CHROMEOS_CSE_BOARD_RESET_OVERRIDE
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select CHROMEOS_CSE_BOARD_RESET_OVERRIDE
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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@ -21,16 +21,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
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memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
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memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
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}
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}
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const char *mainboard_get_dram_part_num(void)
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{
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static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
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if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0],
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sizeof(part_num_store)) < 0) {
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printk(BIOS_ERR, "No DRAM part number in CBI!\n");
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return NULL;
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}
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return part_num_store;
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}
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@ -47,6 +47,7 @@ if BOARD_GOOGLE_HATCH_COMMON
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config CHROMEOS
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config CHROMEOS
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bool
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bool
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default y
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default y
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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@ -56,28 +56,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
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cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
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cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
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}
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}
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const char *mainboard_get_dram_part_num(void)
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{
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static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
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static enum {
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PART_NUM_NOT_READ,
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PART_NUM_AVAILABLE,
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PART_NUM_NOT_IN_CBI,
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} part_num_state = PART_NUM_NOT_READ;
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if (part_num_state == PART_NUM_NOT_READ) {
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if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0],
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sizeof(part_num_store)) < 0) {
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printk(BIOS_ERR, "No DRAM part number in CBI!\n");
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part_num_state = PART_NUM_NOT_IN_CBI;
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} else {
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part_num_state = PART_NUM_AVAILABLE;
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}
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}
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if (part_num_state == PART_NUM_NOT_IN_CBI)
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return NULL;
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return part_num_store;
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}
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@ -35,6 +35,7 @@ config CHROMEOS
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bool
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bool
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default y
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default y
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select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
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select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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@ -28,15 +28,3 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated);
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meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated);
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}
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}
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const char *mainboard_get_dram_part_num(void)
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{
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static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
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if (google_chromeec_cbi_get_dram_part_num(part_num_store,
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sizeof(part_num_store)) < 0) {
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printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n");
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return NULL;
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}
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return part_num_store;
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}
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