boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEX
These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -21,10 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config MAINBOARD_DIR
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string
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default google/bolt
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@ -44,10 +44,6 @@ config MAINBOARD_VENDOR
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string
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default "Google"
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -24,10 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config MAINBOARD_DIR
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string
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default google/falco
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@ -81,10 +81,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 1
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config FLASHMAP_OFFSET
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hex
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default 0x00100000
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@ -82,10 +82,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 1
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config FLASHMAP_OFFSET
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hex
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default 0x00100000
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@ -83,10 +83,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 1
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config FLASHMAP_OFFSET
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hex
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default 0x00100000
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@ -21,10 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select PHYSICAL_REC_SWITCH
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x1
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config MAINBOARD_DIR
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string
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default google/panther
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@ -26,10 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config MAINBOARD_DIR
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string
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default google/peppy
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@ -15,14 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
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select ALWAYS_LOAD_OPROM
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config VBOOT_REFCODE_INDEX
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hex
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default 0x3
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config MAINBOARD_DIR
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string
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default google/rambi
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@ -82,13 +82,6 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
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help
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Which chip select to use for boot media.
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# For rush, we are using vboot2. Thus, index for stages:
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# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
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# VBOOT_RAMSTAGE_INDEX -> Use 0x3
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x2
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@ -79,13 +79,6 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
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help
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Which chip select to use for boot media.
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# For ryu, we are using vboot2. Thus, index for stages:
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# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
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# VBOOT_RAMSTAGE_INDEX -> Use 0x3
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x2
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@ -21,14 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config VBOOT_REFCODE_INDEX
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hex
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default 0x4
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config MAINBOARD_DIR
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string
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default google/samus
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@ -23,10 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config MAINBOARD_DIR
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string
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default google/slippy
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@ -49,17 +49,6 @@ config MAINBOARD_VENDOR
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string
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default "Google"
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# The 'ecrwhash' is removed from FMAP on Brain, since we don't have EC.
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# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
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# better approaches for vboot2 to find right index.
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config VBOOT_ROMSTAGE_INDEX
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hex
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default 0x1
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -49,17 +49,6 @@ config MAINBOARD_VENDOR
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string
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default "Google"
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# The 'ecrwhash' is removed from FMAP on Danger, since we don't have EC.
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# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
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# better approaches for vboot2 to find right index.
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config VBOOT_ROMSTAGE_INDEX
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hex
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default 0x1
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
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int
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default 100
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
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int
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default 100
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
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int
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default 100
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -48,17 +48,6 @@ config MAINBOARD_VENDOR
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string
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default "Google"
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# The 'ecrwhash' is removed from FMAP on Rialto, since we don't have EC.
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# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
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# better approaches for vboot2 to find right index.
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config VBOOT_ROMSTAGE_INDEX
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hex
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default 0x1
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
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int
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default 100
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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@ -16,14 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CHROMEOS_RAMOOPS_DYNAMIC
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select CHROMEOS_VBNV_CMOS
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x1
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config VBOOT_REFCODE_INDEX
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hex
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default 0x2
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config MAINBOARD_DIR
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string
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default intel/wtm2
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