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boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEX 

These options will need to just be selected in within
the .config files. There's not need in duplicating all
these options.

Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9959
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2015-04-22 10:48:01 -05:00 committed by Patrick Georgi
parent 1124cec59a
commit be3e0a04b5
21 changed files with 0 additions and 123 deletions
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4
src/mainboard/google/bolt/Kconfig
View File

@ -21,10 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_INT15 select INTEL_INT15
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default google/bolt default google/bolt

4
src/mainboard/google/cosmos/Kconfig
View File

@ -44,10 +44,6 @@ config MAINBOARD_VENDOR
string string
default "Google" default "Google"
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

4
src/mainboard/google/falco/Kconfig
View File

@ -24,10 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_INT15 select INTEL_INT15
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default google/falco default google/falco

4
src/mainboard/google/nyan/Kconfig
View File

@ -81,10 +81,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 1
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config FLASHMAP_OFFSET config FLASHMAP_OFFSET
hex hex
default 0x00100000 default 0x00100000

4
src/mainboard/google/nyan_big/Kconfig
View File

@ -82,10 +82,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 1
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config FLASHMAP_OFFSET config FLASHMAP_OFFSET
hex hex
default 0x00100000 default 0x00100000

4
src/mainboard/google/nyan_blaze/Kconfig
View File

@ -83,10 +83,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 1
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config FLASHMAP_OFFSET config FLASHMAP_OFFSET
hex hex
default 0x00100000 default 0x00100000

4
src/mainboard/google/panther/Kconfig
View File

@ -21,10 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select PHYSICAL_REC_SWITCH select PHYSICAL_REC_SWITCH
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x1
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default google/panther default google/panther

4
src/mainboard/google/peppy/Kconfig
View File

@ -26,10 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_INT15 select INTEL_INT15
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default google/peppy default google/peppy

8
src/mainboard/google/rambi/Kconfig
View File

@ -15,14 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
select ALWAYS_LOAD_OPROM select ALWAYS_LOAD_OPROM
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config VBOOT_REFCODE_INDEX
hex
default 0x3
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default google/rambi default google/rambi

7
src/mainboard/google/rush/Kconfig
View File

@ -82,13 +82,6 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
help help
Which chip select to use for boot media. Which chip select to use for boot media.
# For rush, we are using vboot2. Thus, index for stages:
# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
# VBOOT_RAMSTAGE_INDEX -> Use 0x3
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex
default 0x2 default 0x2

7
src/mainboard/google/rush_ryu/Kconfig
View File

@ -79,13 +79,6 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
help help
Which chip select to use for boot media. Which chip select to use for boot media.
# For ryu, we are using vboot2. Thus, index for stages:
# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
# VBOOT_RAMSTAGE_INDEX -> Use 0x3
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex
default 0x2 default 0x2

8
src/mainboard/google/samus/Kconfig
View File

@ -21,14 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_INT15 select INTEL_INT15
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config VBOOT_REFCODE_INDEX
hex
default 0x4
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default google/samus default google/samus

4
src/mainboard/google/slippy/Kconfig
View File

@ -23,10 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_INT15 select INTEL_INT15
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default google/slippy default google/slippy

11
src/mainboard/google/veyron_brain/Kconfig
View File

@ -49,17 +49,6 @@ config MAINBOARD_VENDOR
string string
default "Google" default "Google"
# The 'ecrwhash' is removed from FMAP on Brain, since we don't have EC.
# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
# better approaches for vboot2 to find right index.
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config VBOOT_ROMSTAGE_INDEX
hex
default 0x1
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

11
src/mainboard/google/veyron_danger/Kconfig
View File

@ -49,17 +49,6 @@ config MAINBOARD_VENDOR
string string
default "Google" default "Google"
# The 'ecrwhash' is removed from FMAP on Danger, since we don't have EC.
# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
# better approaches for vboot2 to find right index.
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config VBOOT_ROMSTAGE_INDEX
hex
default 0x1
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

4
src/mainboard/google/veyron_jerry/Kconfig
View File

@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int int
default 100 default 100
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

4
src/mainboard/google/veyron_mighty/Kconfig
View File

@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int int
default 100 default 100
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

4
src/mainboard/google/veyron_pinky/Kconfig
View File

@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int int
default 100 default 100
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

11
src/mainboard/google/veyron_rialto/Kconfig
View File

@ -48,17 +48,6 @@ config MAINBOARD_VENDOR
string string
default "Google" default "Google"
# The 'ecrwhash' is removed from FMAP on Rialto, since we don't have EC.
# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
# better approaches for vboot2 to find right index.
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
config VBOOT_ROMSTAGE_INDEX
hex
default 0x1
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

4
src/mainboard/google/veyron_speedy/Kconfig
View File

@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int int
default 100 default 100
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2

8
src/mainboard/intel/wtm2/Kconfig
View File

@ -16,14 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CHROMEOS_RAMOOPS_DYNAMIC select CHROMEOS_RAMOOPS_DYNAMIC
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS
config VBOOT_RAMSTAGE_INDEX
hex
default 0x1
config VBOOT_REFCODE_INDEX
hex
default 0x2
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default intel/wtm2 default intel/wtm2