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soc/intel/alderlake: Configure DDR5 Physical channel width to 64 

A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.

BUG=b:180458099
TEST=Boot DDR5 to kernel

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Meera Ravindranath 2021-04-28 15:02:47 +05:30 committed by Felix Held
parent b85997df25
commit be5dc3daa0
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/alderlake/meminit.c
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@ -11,7 +11,7 @@
#define DDR4_PHYSICAL_CH_WIDTH 64
#define DDR4_CHANNELS CHANNEL_COUNT(DDR4_PHYSICAL_CH_WIDTH)
#define DDR5_PHYSICAL_CH_WIDTH 32
#define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */
#define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg)