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support for different location of HT registers in old version of K8T800 

Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/373
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Florian Zumbiehl 2011-11-01 20:17:14 +01:00 committed by Stefan Reinauer
parent 583abc2eb2
commit be7d8dcf8d
1 changed files with 22 additions and 8 deletions
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30
src/southbridge/via/k8t890/early_car.c
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@ -35,6 +35,12 @@
/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
#define K8X8XX_HT_CFG_BASE 0xc0
#else
#define K8X8XX_HT_CFG_BASE 0x60
#endif
/* This functions sets KT890 link frequency and width to same values as
* it has been setup on K8 side, by AMD NB init.
* This will not work for K8T800_OLD, which has a slightly different
@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
u8 k8t890_early_setup_ht(void)
{
u8 awidth, afreq, cldtfreq, reg;
u8 awidth, afreq, cldtfreq;
u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
u16 vldtcaps;
#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
u8 reg;
/* hack, enable NVRAM in chipset */
pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void)
reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
reg |= 0x1;
pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
#endif
/* check if connected non coherent, initcomplete (find the SB on K8 side) */
ldtnr = 0;
@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void)
print_debug("K8M800 found at LDT ");
#elif CONFIG_SOUTHBRIDGE_VIA_K8T800
print_debug("K8T800 found at LDT ");
#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
print_debug("K8T800_OLD found at LDT ");
pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00);
pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50);
#elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO
print_debug("K8T800 Pro found at LDT ");
#elif CONFIG_SOUTHBRIDGE_VIA_K8M890
@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void)
/* get the maximum widths for both sides */
cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7;
cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7;
vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7;
vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7;
vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7;
vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7;
width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in);
print_debug(" Agreed on width: ");
print_debug_hex8(width);
awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67);
awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7);
/* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */
width = (width == 0x01) ? 0x11 : 0x00;
pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width);
pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width);
/* Get programmed HT freq at base 0x89 */
cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf;
@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void)
print_debug_hex8(cldtfreq);
print_debug(" VIA HT caps: ");
vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e);
vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe);
print_debug_hex16(vldtcaps);
if (!(vldtcaps & (1 << cldtfreq ))) {
die("Chipset does not support desired HT frequency\n");
}
afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d);
pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq);
afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd);
pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq);
print_debug("\n");
/* no reset needed */