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soc/mediatek/mt8195: Disable UFS reference clock

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UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.
Change UFSHCI base register to 0x11270000.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Yidi Lin 2021-04-19 16:06:55 +08:00 committed by Hung-Te Lin
parent 9a05601341
commit be8621d785
3 changed files with 4 additions and 1 deletions
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1
src/soc/mediatek/mt8195/Makefile.inc
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@ -47,6 +47,7 @@ ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += soc.c ramstage-y += soc.c
ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/timer.c timer.c
ramstage-y += ../common/uart.c ramstage-y += ../common/uart.c
ramstage-y += ../common/ufs.c
ramstage-y += ../common/usb.c usb.c ramstage-y += ../common/usb.c usb.c
ramstage-y += ../common/wdt.c ramstage-y += ../common/wdt.c
ramstage-y += mt6360.c ramstage-y += mt6360.c

2
src/soc/mediatek/mt8195/include/soc/addressmap.h
View file

@ -61,6 +61,7 @@ enum {
SPIS1_BASE = IO_PHYS + 0x0101E000, SPIS1_BASE = IO_PHYS + 0x0101E000,
SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00,
MSDC0_BASE = IO_PHYS + 0x01230000, MSDC0_BASE = IO_PHYS + 0x01230000,
UFSHCI_BASE = IO_PHYS + 0x01270000,
SFLASH_REG_BASE = IO_PHYS + 0x0132C000, SFLASH_REG_BASE = IO_PHYS + 0x0132C000,
EFUSEC_BASE = IO_PHYS + 0x01C10000, EFUSEC_BASE = IO_PHYS + 0x01C10000,
MIPITX_BASE = IO_PHYS + 0x01C80000, MIPITX_BASE = IO_PHYS + 0x01C80000,
@ -73,7 +74,6 @@ enum {
IOCFG_RB_BASE = IO_PHYS + 0x01EB0000, IOCFG_RB_BASE = IO_PHYS + 0x01EB0000,
IOCFG_TL_BASE = IO_PHYS + 0x01F40000, IOCFG_TL_BASE = IO_PHYS + 0x01F40000,
MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000,
UFSHCI_BASE = IO_PHYS + 0x01FA0000,
DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000,
DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000,
DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000,

2
src/soc/mediatek/mt8195/soc.c
View file

@ -3,6 +3,7 @@
#include <device/device.h> #include <device/device.h>
#include <soc/emi.h> #include <soc/emi.h>
#include <soc/mmu_operations.h> #include <soc/mmu_operations.h>
#include <soc/ufs.h>
#include <symbols.h> #include <symbols.h>
static void soc_read_resources(struct device *dev) static void soc_read_resources(struct device *dev)
@ -13,6 +14,7 @@ static void soc_read_resources(struct device *dev)
static void soc_init(struct device *dev) static void soc_init(struct device *dev)
{ {
mtk_mmu_disable_l2c_sram(); mtk_mmu_disable_l2c_sram();
ufs_disable_refclk();
} }
static struct device_operations soc_ops = { static struct device_operations soc_ops = {