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Program the I/O APIC ID. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 21:41:00 +00:00 committed by Marc Jones
parent f191c72038
commit be8fae1c71
1 changed files with 19 additions and 0 deletions
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19
src/southbridge/amd/cimx_wrapper/sb800/late.c
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@ -352,6 +352,25 @@ static void sb800_enable(device_t dev)
break; break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
{
u8 byte;
u32 ioapic_base;
printk(BIOS_INFO, "sm_init().\n");
ioapic_base = 0xFEC00000;
clear_ioapic(ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(ioapic_base, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
}
break; break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */ case (0x14 << 3) | 1: /* 0:14:1 IDE */