mb/gigabyte/ga-945gcm-s2l: add mainboard
Startpoint was Intel d945gclf, which has same chipset and Gigabyte ga-g41m-es2l which has same Superio. What works and is tested: * PCI slot; * PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card; * onboard VGA output (only textmode implemented) with native graphic init; * 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset); * serial output during and after boot. What does not work: * resume from suspend (does not work for d945gclf either). Quirks: * The Realtek ethernet card requires a reset which currently also hardcodes a MAC adress. This board was only tested with the SeaBIOS payload due to flash size constraints (512KB) and with GNU/Linux. Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17033 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
4c5b31e567
commit
be91398353
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@ -0,0 +1,58 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 coresystems GmbH
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## Copyright (C) 2016 Arthur Heymans <arthur@ahemans.xyz
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_GIGABYTE_GA_945GCM_S2L
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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select CHECK_SLFRCS_ON_RESUME
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select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_ITE_IT8718F
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_RESUME
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select BOARD_ROMSIZE_KB_512
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select CHANNEL_XOR_RANDOMIZATION
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select INTEL_EDID
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select REALTEK_8168_RESET
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config MAINBOARD_DIR
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string
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default gigabyte/ga-945gcm-s2l
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config MAINBOARD_PART_NUMBER
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string
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default "GA-945GCM-S2L"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAX_CPUS
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int
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default 2
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endif # BOARD_GIGABYTE_GA_945GCM_S2L
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@ -0,0 +1,2 @@
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config BOARD_GIGABYTE_GA_945GCM_S2L
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bool "GA-945GCM-S2L"
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@ -0,0 +1 @@
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ramstage-y += cstates.c
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@ -0,0 +1,51 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device(EC0)
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{
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Name (_HID, EISAID("PNP0C09"))
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Name (_UID, 1)
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// _REG method requires that an operation region be defined.
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OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
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Field (ERAM, ByteAcc, Lock, Preserve)
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{
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}
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Method (_CRS, 0, Serialized)
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{
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Name (ECMD, ResourceTemplate()
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{
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IO (Decode16, 0x62, 0x62, 0, 1)
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IO (Decode16, 0x66, 0x66, 0, 1)
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})
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Return (ECMD)
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}
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Method (_REG, 2)
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{
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// This method is needed by Windows XP/2000
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// for EC initialization before a driver
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// is loaded
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}
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Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
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// TODO EC Query methods
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// TODO Scope _SB devices for AC power, LID, Power button
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}
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@ -0,0 +1,75 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for the
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* i945
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*/
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, 0, 16 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 16 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, 0, 16 },
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Package() { 0x001dffff, 1, 0, 17 },
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Package() { 0x001dffff, 2, 0, 18 },
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Package() { 0x001dffff, 3, 0, 19 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, 0, 16 },
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Package() { 0x001fffff, 1, 0, 17 },
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Package() { 0x001fffff, 2, 0, 18 },
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Package() { 0x001fffff, 3, 0, 19 },
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})
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} Else {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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})
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}
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for the
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* 0:1e.0 PCI bridge of the ICH7
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*/
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If (PICM) {
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Return (Package() {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x14 },
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
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Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x13 },
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Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x12 },
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Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x10 },
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Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 },
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})
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} Else {
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Return (Package() {
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Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKA, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
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})
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}
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@ -0,0 +1,30 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (SLPB)
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{
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Name(_HID, EisaId("PNP0C0E"))
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// Wake
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Name(_PRW, Package(){0x1d, 0x04})
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}
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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// Wake
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Name(_PRW, Package(){0x1d, 0x04})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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// Call a trap so SMI can prepare for Sleep as well.
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// TRAP(0x55)
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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// CPU specific part
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// Notify PCI Express slots in case a card
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// was inserted while a sleep state was active.
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// Are we going to S3?
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If (LEqual(Arg0, 3)) {
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// ..
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}
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// Are we going to S4?
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If (LEqual(Arg0, 4)) {
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// ..
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}
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// TODO: Windows XP SP2 P-State restore
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Return(Package(){0,0})
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}
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/* dummy */
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@ -0,0 +1 @@
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/* dummy */
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/*
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* This file is part of the coreboot project.
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*
|
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* Copyright (C) 2007-2009 coresystems GmbH
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*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
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*
|
||||
* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include <types.h>
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#include <string.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <arch/ioapic.h>
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#include "southbridge/intel/i82801gx/nvs.h"
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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}
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@ -0,0 +1,6 @@
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Category: desktop
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Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2669#ov
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Release year: 2007
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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boot_option=Fallback
|
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baud_rate=115200
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debug_level=Spew
|
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hyper_threading=Enable
|
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nmi=Enable
|
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boot_devices=''
|
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gfx_uma_size=8M
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|
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#
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# This file is part of the coreboot project.
|
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#
|
||||
# Copyright (C) 2007-2008 coresystems GmbH
|
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#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
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|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
|
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#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
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#103 1 r 0 irqf_flag
|
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# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
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#111 1 r 0 valid_cmos_ram
|
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# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
400 1 e 2 hyper_threading
|
||||
#401 7 r 0 unused
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
# coreboot config options: northbridge
|
||||
411 3 e 11 gfx_uma_size
|
||||
|
||||
# coreboot config options: bootloader
|
||||
416 512 s 0 boot_devices
|
||||
#928 80 r 0 unused
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
#1000 24 r 0 amd_reserved
|
||||
|
||||
# RAM initialization internal data
|
||||
1024 8 r 0 C0WL0REOST
|
||||
1032 8 r 0 C1WL0REOST
|
||||
1040 8 r 0 RCVENMT
|
||||
1048 4 r 0 C0DRT1
|
||||
1052 4 r 0 C1DRT1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
11 0 1M
|
||||
11 1 4M
|
||||
11 2 8M
|
||||
11 3 16M
|
||||
11 4 32M
|
||||
11 5 48M
|
||||
11 6 64M
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <arch/x86/include/arch/acpigen.h>
|
||||
|
||||
int get_cst_entries(acpi_cstate_t **entries)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2009 coresystems GmbH
|
||||
## Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
chip northbridge/intel/i945
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_LGA775
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/model_1067x
|
||||
device lapic 0xACAC off end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on # host bridge
|
||||
subsystemid 0x1458 0x5000
|
||||
end
|
||||
device pci 01.0 on # i945 PCIe root port
|
||||
subsystemid 0x1458 0x5000
|
||||
ioapic_irq 2 INTA 0x10
|
||||
end
|
||||
device pci 02.0 on # vga controller
|
||||
subsystemid 0x1458 0xd000
|
||||
ioapic_irq 2 INTA 0x10
|
||||
end
|
||||
|
||||
chip southbridge/intel/i82801gx
|
||||
register "pirqa_routing" = "0x8c"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x83"
|
||||
register "pirqd_routing" = "0x8b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x85"
|
||||
|
||||
# GPI routing
|
||||
# 0 No effect (default)
|
||||
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
|
||||
# 2 SCI (if corresponding GPIO_EN bit is also set)
|
||||
register "gpi0_routing" = "1"
|
||||
register "gpi1_routing" = "1"
|
||||
register "gpi2_routing" = "1"
|
||||
register "gpi3_routing" = "1"
|
||||
register "gpi4_routing" = "1"
|
||||
register "gpi5_routing" = "1"
|
||||
register "gpi6_routing" = "1"
|
||||
register "gpi7_routing" = "1"
|
||||
register "gpi8_routing" = "1"
|
||||
register "gpi9_routing" = "1"
|
||||
register "gpi10_routing" = "1"
|
||||
register "gpi11_routing" = "1"
|
||||
register "gpi12_routing" = "1"
|
||||
register "gpi13_routing" = "2"
|
||||
register "gpi14_routing" = "1"
|
||||
register "gpi15_routing" = "1"
|
||||
|
||||
register "gpe0_en" = "0"
|
||||
|
||||
register "ide_legacy_combined" = "0x0"
|
||||
register "ide_enable_primary" = "0x1"
|
||||
register "ide_enable_secondary" = "0x0"
|
||||
register "sata_ahci" = "0x0"
|
||||
register "c3_latency" = "85"
|
||||
|
||||
register "p_cnt_throttling_supported" = "0"
|
||||
|
||||
device pci 1b.0 on # High Definition Audio
|
||||
ioapic_irq 2 INTA 0x10
|
||||
end
|
||||
device pci 1c.0 on end # PCIe
|
||||
device pci 1c.1 on end # PCIe
|
||||
#device pci 1c.2 off end # PCIe port 3
|
||||
#device pci 1c.3 off end # PCIe port 4
|
||||
#device pci 1c.4 off end # PCIe port 5
|
||||
#device pci 1c.5 off end # PCIe port 6
|
||||
device pci 1d.0 on # USB UHCI
|
||||
ioapic_irq 2 INTA 0x10
|
||||
end
|
||||
device pci 1d.1 on # USB UHCI
|
||||
ioapic_irq 2 INTB 0x11
|
||||
end
|
||||
device pci 1d.2 on # USB UHCI
|
||||
ioapic_irq 2 INTC 0x12
|
||||
end
|
||||
device pci 1d.3 on # USB UHCI
|
||||
ioapic_irq 2 INTD 0x13
|
||||
end
|
||||
device pci 1d.7 on # USB2 EHCI
|
||||
ioapic_irq 2 INTA 0x10
|
||||
end
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
|
||||
device pci 1f.0 on # LPC bridge
|
||||
ioapic_irq 2 INTA 0x10
|
||||
chip superio/ite/it8718f # Super I/O
|
||||
device pnp 2e.0 off end # Floppy
|
||||
device pnp 2e.1 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off end # COM2
|
||||
device pnp 2e.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
io 0x62 = 0
|
||||
drq 0x74 = 4
|
||||
irq 0xf0 = 0x08
|
||||
end
|
||||
device pnp 2e.4 on # Environment controller
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 0x00
|
||||
io 0x62 = 0x000
|
||||
irq 0xf0 = 0x00
|
||||
irq 0xf1 = 0x00
|
||||
irq 0xf2 = 0x0a
|
||||
irq 0xf3 = 0x00
|
||||
irq 0xf4 = 0x80
|
||||
irq 0xf5 = 0x20
|
||||
irq 0xf6 = 0x3e
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
irq 0x70 = 1
|
||||
io 0x62 = 0x64
|
||||
irq 0xf0 = 0x48
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 0
|
||||
irq 0x71 = 2
|
||||
irq 0xf0 = 0
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on # IDE
|
||||
ioapic_irq 2 INTB 0x11
|
||||
end
|
||||
device pci 1f.2 on # SATA
|
||||
ioapic_irq 2 INTC 0x12
|
||||
end
|
||||
device pci 1f.3 on # SMBus
|
||||
ioapic_irq 2 INTD 0x13
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20090419 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/common/acpi/platform.asl>
|
||||
|
||||
// General Purpose Events
|
||||
//#include "acpi/gpe.asl"
|
||||
|
||||
// mainboard specific devices
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
// Thermal Zone
|
||||
//#include "acpi/thermal.asl"
|
||||
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/i945/acpi/i945.asl>
|
||||
#include <southbridge/intel/i82801gx/acpi/ich7.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0662, /* Vendor ID */
|
||||
0x1458a002, /* Subsystem ID */
|
||||
0x00000009, /* Number of entries */
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19830),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x014b6120),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
* Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <lib.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cbmem.h>
|
||||
#include <superio/ite/it8718f/it8718f.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/intel/romstage.h>
|
||||
#include <northbridge/intel/i945/i945.h>
|
||||
#include <northbridge/intel/i945/raminit.h>
|
||||
#include <southbridge/intel/i82801gx/i82801gx.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
|
||||
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
|
||||
#define EC_DEV PNP_DEV(0x2e, IT8718F_EC)
|
||||
#define SUPERIO_DEV PNP_DEV(0x2e, 0)
|
||||
|
||||
void setup_ich7_gpios(void)
|
||||
{
|
||||
/* TODO: This is highly board specific and should be moved */
|
||||
printk(BIOS_DEBUG, " GPIOS...");
|
||||
/* General Registers */
|
||||
outl(0x1f15f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
|
||||
outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
|
||||
outl(0xe2fefc03, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
|
||||
/* Output Control Registers */
|
||||
outl(0x00400000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
|
||||
/* Input Control Registers */
|
||||
outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
|
||||
outl(0x000000c7, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
|
||||
outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
|
||||
outl(0x000000f2, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
|
||||
}
|
||||
|
||||
static void setup_sio(void)
|
||||
{
|
||||
/* Set default GPIOs on superio */
|
||||
ite_reg_write(GPIO_DEV, 0x25, 0x40);
|
||||
ite_reg_write(GPIO_DEV, 0x26, 0x3f);
|
||||
ite_reg_write(GPIO_DEV, 0x28, 0x41);
|
||||
ite_reg_write(GPIO_DEV, 0x29, 0x88);
|
||||
ite_reg_write(GPIO_DEV, 0x2c, 0x1c);
|
||||
ite_reg_write(GPIO_DEV, 0x62, 0x08);
|
||||
ite_reg_write(GPIO_DEV, 0x72, 0x00);
|
||||
ite_reg_write(GPIO_DEV, 0x73, 0x38);
|
||||
ite_reg_write(GPIO_DEV, 0xb1, 0x01);
|
||||
ite_reg_write(GPIO_DEV, 0xb8, 0x80);
|
||||
ite_reg_write(GPIO_DEV, 0xbb, 0x40);
|
||||
ite_reg_write(GPIO_DEV, 0xc0, 0x00);
|
||||
ite_reg_write(GPIO_DEV, 0xc3, 0x00);
|
||||
ite_reg_write(GPIO_DEV, 0xc8, 0x00);
|
||||
ite_reg_write(GPIO_DEV, 0xcb, 0x00);
|
||||
ite_reg_write(GPIO_DEV, 0xf6, 0x26);
|
||||
ite_reg_write(GPIO_DEV, 0xfc, 0x4a);
|
||||
|
||||
ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
|
||||
ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
|
||||
}
|
||||
|
||||
static void ich7_enable_lpc(void)
|
||||
{
|
||||
// Enable Serial IRQ
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
|
||||
// Set COM1/COM2 decode range
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
|
||||
// Enable COM1
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d);
|
||||
// Enable SuperIO Power Management Events
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
|
||||
}
|
||||
|
||||
static void rcba_config(void)
|
||||
{
|
||||
/* Enable IOAPIC */
|
||||
RCBA8(0x31ff) = 0x03;
|
||||
|
||||
/* Disable unused devices */
|
||||
RCBA32(0x3418) = 0x003c0061;
|
||||
|
||||
/* Enable PCIe Root Port Clock Gate */
|
||||
RCBA32(0x341c) = 0x00000001;
|
||||
}
|
||||
|
||||
static void early_ich7_init(void)
|
||||
{
|
||||
uint8_t reg8;
|
||||
uint32_t reg32;
|
||||
|
||||
// program secondary mlt XXX byte?
|
||||
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
|
||||
|
||||
// reset rtc power status
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
|
||||
reg8 &= ~(1 << 2);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
|
||||
|
||||
// usb transient disconnect
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
|
||||
reg8 |= (3 << 0);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
|
||||
|
||||
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
|
||||
reg32 |= (1 << 29) | (1 << 17);
|
||||
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
|
||||
|
||||
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
|
||||
reg32 |= (1 << 31) | (1 << 27);
|
||||
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
|
||||
|
||||
RCBA32(0x0088) = 0x0011d000;
|
||||
RCBA16(0x01fc) = 0x060f;
|
||||
RCBA32(0x01f4) = 0x86000040;
|
||||
RCBA32(0x0214) = 0x10030509;
|
||||
RCBA32(0x0218) = 0x00020504;
|
||||
RCBA8(0x0220) = 0xc5;
|
||||
reg32 = RCBA32(0x3410);
|
||||
reg32 |= (1 << 6);
|
||||
RCBA32(0x3410) = reg32;
|
||||
reg32 = RCBA32(0x3430);
|
||||
reg32 &= ~(3 << 0);
|
||||
reg32 |= (1 << 0);
|
||||
RCBA32(0x3430) = reg32;
|
||||
RCBA32(0x3418) |= (1 << 0);
|
||||
RCBA16(0x0200) = 0x2008;
|
||||
RCBA8(0x2027) = 0x0d;
|
||||
RCBA16(0x3e08) |= (1 << 7);
|
||||
RCBA16(0x3e48) |= (1 << 7);
|
||||
RCBA32(0x3e0e) |= (1 << 7);
|
||||
RCBA32(0x3e4e) |= (1 << 7);
|
||||
|
||||
// next step only on ich7m b0 and later:
|
||||
reg32 = RCBA32(0x2034);
|
||||
reg32 &= ~(0x0f << 16);
|
||||
reg32 |= (5 << 16);
|
||||
RCBA32(0x2034) = reg32;
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
int s3resume = 0, boot_mode = 0;
|
||||
|
||||
if (bist == 0)
|
||||
enable_lapic();
|
||||
|
||||
ich7_enable_lpc();
|
||||
/* Enable SuperIO PM */
|
||||
setup_sio();
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
/* Disable SIO reboot */
|
||||
ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
|
||||
|
||||
/* Set up the console */
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
if (MCHBAR16(SSKPD) == 0xCAFE) {
|
||||
printk(BIOS_DEBUG, "soft reset detected.\n");
|
||||
boot_mode = 1;
|
||||
}
|
||||
|
||||
/* Perform some early chipset initialization required
|
||||
* before RAM initialization can work
|
||||
*/
|
||||
i945_early_initialization();
|
||||
|
||||
s3resume = southbridge_detect_s3_resume();
|
||||
|
||||
/* Enable SPD ROMs and DDR-II DRAM */
|
||||
enable_smbus();
|
||||
|
||||
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
|
||||
|
||||
/* Perform some initialization that must run before stage2 */
|
||||
early_ich7_init();
|
||||
|
||||
/* This should probably go away. Until now it is required
|
||||
* and mainboard specific
|
||||
*/
|
||||
rcba_config();
|
||||
|
||||
/* Chipset Errata! */
|
||||
fixup_i945_errata();
|
||||
|
||||
/* Initialize the internal PCIe links before we go into stage2 */
|
||||
i945_late_initialization(s3resume);
|
||||
}
|
||||
Loading…
Reference in New Issue