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mb/google/fizz/endeavour/gpio: Reflow long lines 

Use the 96 character limit.

Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Maxim Polyakov 2020-08-12 12:50:46 +03:00 committed by Michael Niewöhner
parent ac17fad84e
commit be96c62b1e
1 changed files with 30 additions and 60 deletions
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90
src/mainboard/google/fizz/variants/endeavour/gpio.c
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@ -14,15 +14,13 @@ static const struct pad_config gpio_table[] = {
/* ESPI_IO3 */ /* ESPI_IO3 */
/* ESPI_CS# */ /* ESPI_CS# */
/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ /* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */
/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, /* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, EDGE), /* SD_CDZ */
EDGE), /* SD_CDZ */
/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ /* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */
/* ESPI_CLK */ /* ESPI_CLK */
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */
/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ /* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */
/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), /* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */
DEEP), /* eSPI mode */
/* ESPI_RESET# */ /* ESPI_RESET# */
/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ /* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
@ -39,30 +37,20 @@ static const struct pad_config gpio_table[] = {
/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ /* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */
/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), /* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), /* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */
NF1), /* CLK_PCIE_LAN_REQ# */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU# */
NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* PCIE_CLKREQ_POE# */
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU1# */
NF1), /* PCIE_CLKREQ_TPU# */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */
/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP,
NF1), /* PCIE_CLKREQ_POE# */
/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP,
NF1), /* PCIE_CLKREQ_TPU1# */
/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,
NF1), /* PCIE_CLKREQ_WLAN# */
/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */
NF1), /* PCH_SPI_H1_3V3_CS_L */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CLK */
/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MISO */
NF1), /* PCH_SPI_H1_3V3_CLK */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */
/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
NF1), /* PCH_SPI_H1_3V3_MISO */
/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
NF1), /* PCH_SPI_H1_3V3_MOSI */
/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */ /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */
/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), /* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), /* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
@ -75,21 +63,16 @@ static const struct pad_config gpio_table[] = {
/* SML0CLK */ PAD_CFG_NC(GPP_C3), /* SML0CLK */ PAD_CFG_NC(GPP_C3),
/* SML0DATA */ PAD_CFG_NC(GPP_C4), /* SML0DATA */ PAD_CFG_NC(GPP_C4),
/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, /* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
DEEP), /* EC_IN_RW */
/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */ /* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */
/* UART0_RXD */ PAD_CFG_NC(GPP_C8), /* UART0_RXD */ PAD_CFG_NC(GPP_C8),
/* UART0_TXD */ PAD_CFG_NC(GPP_C9), /* UART0_TXD */ PAD_CFG_NC(GPP_C9),
/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), /* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */
DEEP), /* SKU_ID0 */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* SKU_ID1 */
/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* SKU_ID2 */
DEEP), /* SKU_ID1 */ /* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* SKU_ID3 */
/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
DEEP), /* SKU_ID2 */
/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
DEEP), /* SKU_ID3 */
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */
@ -97,8 +80,7 @@ static const struct pad_config gpio_table[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */ /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */
/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */
DEEP), /* SCREW_SPI_WP_STATUS */
/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */ /* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */
/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */ /* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */
@ -109,14 +91,10 @@ static const struct pad_config gpio_table[] = {
/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), /* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, /* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */
PLTRST, EDGE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */
/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */
DEEP), /* OEM_ID1 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */
/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,
DEEP), /* OEM_ID2 */
/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,
DEEP), /* OEM_ID3 */
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
@ -129,10 +107,8 @@ static const struct pad_config gpio_table[] = {
/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */ /* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */
PLTRST), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
NF1), /* MB_PCIE_SATA#_DET */
/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
/* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, /* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP,
NONE), /* TPU_RST_PIN40 */ NONE), /* TPU_RST_PIN40 */
@ -144,14 +120,10 @@ static const struct pad_config gpio_table[] = {
/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */
/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ /* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */
/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */
NF1), /* Rear Dual-Stack USB Ports */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */
/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI1_HDMI_HPD */
NF1), /* Rear Single USB Port */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HDMI_HPD */
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,
NF1), /* DDI1_HDMI_HPD */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
NF1), /* DDI2_HDMI_HPD */
/* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ /* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */
/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */ /* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
@ -172,10 +144,8 @@ static const struct pad_config gpio_table[] = {
/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */ /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */
/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), /* I2C4_SDA */ PAD_CFG_NC(GPP_F8),
/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), /* I2C4_SCL */ PAD_CFG_NC(GPP_F9),
/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */
NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,
NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), /* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), /* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), /* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),