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superio/winbond/w83627hf: Avoid .c includes in mainboards 

Move towards the removal of the superio model specific xxx_serial_enable
implementation. Make remaining superio romstage parts link-time symbols
and fix corresponding mainboards to match.

The following mainboards remain unconverted as they are ROMCC:
 - mainboard/supermicro/x6dai_g
 - mainboard/supermicro/x6dhe_g
 - mainboard/supermicro/x6dhr_ig
 - mainboard/supermicro/x6dhr_ig2
and so block the final removal of w83627hf_serial_enable().

Special cases:
 - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
Provide local superio pnp_ programming entry/exit functions as to avoid
making superio implementation global symbols. Although this is not the
proper/final solution, it does mitigate possible symbol collisions and
allow for continued superio refactorisation.

Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5601
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-04-29 13:09:50 +10:00 committed by Kyösti Mälkki
parent 9068788a8f
commit beb0f2631f
17 changed files with 98 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c" #include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h> #include <console/loglevel.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c" #include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c" #include "southbridge/amd/rs780/early_setup.c"
@ -50,6 +51,8 @@
#include <southbridge/amd/cimx/sb800/smbus.h> #include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) static void activate_spd_rom(const struct mem_controller *ctrl)
{ {
} }
@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb800_clk_output_48Mhz(); sb800_clk_output_48Mhz();
w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); w83627hf_set_clksel_48(PNP_DEV(0x2e, 0));
w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");

7
src/mainboard/avalue/eax-785e/romstage.c
View File

@ -41,7 +41,8 @@
#include "northbridge/amd/amdfam10/reset_test.c" #include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h> #include <console/loglevel.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c" #include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c" #include "southbridge/amd/rs780/early_setup.c"
@ -50,6 +51,8 @@
#include <southbridge/amd/cimx/sb800/smbus.h> #include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) static void activate_spd_rom(const struct mem_controller *ctrl)
{ {
} }
@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb800_clk_output_48Mhz(); sb800_clk_output_48Mhz();
w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0));
w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");

5
src/mainboard/msi/ms6178/romstage.c
View File

@ -25,7 +25,8 @@
#include <arch/hlt.h> #include <arch/hlt.h>
#include <stdlib.h> #include <stdlib.h>
#include <console/console.h> #include <console/console.h>
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/i82810/raminit.h" #include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "southbridge/intel/i82801ax/i82801ax.h" #include "southbridge/intel/i82801ax/i82801ax.h"
@ -38,7 +39,7 @@
void main(unsigned long bist) void main(unsigned long bist)
{ {
w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
enable_smbus(); enable_smbus();

5
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -39,7 +39,8 @@
static void cs5536_enable_smbus(void) { } static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/early_setup.c" #include "southbridge/amd/cs5536/early_setup.c"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
/* The part is a Hynix hy5du121622ctp-d43. /* The part is a Hynix hy5du121622ctp-d43.
* *
@ -121,7 +122,7 @@ void main(unsigned long bist)
* It is counting on some early MSR setup for the CS5536. * It is counting on some early MSR setup for the CS5536.
*/ */
cs5536_disable_internal_uart(); cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */

6
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -33,8 +33,8 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include "superio/winbond/w83627hf/early_init.c" #include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/setup_resource_map.c"
@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();

6
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -36,8 +36,8 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include "superio/winbond/w83627hf/early_init.c" #include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/setup_resource_map.c"
@ -115,7 +115,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();

6
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -39,8 +39,8 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdfam10/reset_test.c" #include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include "superio/winbond/w83627hf/early_init.c" #include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c" #include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32); post_code(0x32);
w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();

20
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -39,8 +39,8 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdfam10/reset_test.c" #include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include "superio/winbond/w83627hf/early_init.c" #include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c" #include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -114,6 +114,20 @@ static const u8 spd_addr[] = {
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
/* TODO: superio code should really not be in mainboard */
static void pnp_enter_ext_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
static void pnp_exit_ext_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
}
static void write_GPIO(void) static void write_GPIO(void)
{ {
pnp_enter_ext_func_mode(GPIO1_DEV); pnp_enter_ext_func_mode(GPIO1_DEV);
@ -173,7 +187,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32); post_code(0x32);
w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
write_GPIO(); write_GPIO();

2
src/mainboard/supermicro/x6dai_g/romstage.c
View File

@ -9,13 +9,13 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "southbridge/intel/esb6300/early_smbus.c" #include "southbridge/intel/esb6300/early_smbus.c"
#include "northbridge/intel/e7525/raminit.h" #include "northbridge/intel/e7525/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c" #include "debug.c"
#include "watchdog.c" #include "watchdog.c"
#include "southbridge/intel/esb6300/reset.c" #include "southbridge/intel/esb6300/reset.c"
#include "superio/winbond/w83627hf/early_serial.c" #include "superio/winbond/w83627hf/early_serial.c"
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7525/memory_initialized.c" #include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>

2
src/mainboard/supermicro/x6dhe_g/romstage.c
View File

@ -9,13 +9,13 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "southbridge/intel/esb6300/early_smbus.c" #include "southbridge/intel/esb6300/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h" #include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c" #include "debug.c"
#include "watchdog.c" #include "watchdog.c"
#include "southbridge/intel/esb6300/reset.c" #include "southbridge/intel/esb6300/reset.c"
#include "superio/winbond/w83627hf/early_serial.c" #include "superio/winbond/w83627hf/early_serial.c"
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7520/memory_initialized.c" #include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>

2
src/mainboard/supermicro/x6dhr_ig/romstage.c
View File

@ -7,13 +7,13 @@
#include <console/console.h> #include <console/console.h>
#include "southbridge/intel/i82801ex/early_smbus.c" #include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h" #include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c" #include "debug.c"
#include "watchdog.c" #include "watchdog.c"
#include "southbridge/intel/i82801ex/reset.c" #include "southbridge/intel/i82801ex/reset.c"
#include "superio/winbond/w83627hf/early_serial.c" #include "superio/winbond/w83627hf/early_serial.c"
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7520/memory_initialized.c" #include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>

2
src/mainboard/supermicro/x6dhr_ig2/romstage.c
View File

@ -7,13 +7,13 @@
#include <console/console.h> #include <console/console.h>
#include "southbridge/intel/i82801ex/early_smbus.c" #include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h" #include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c" #include "debug.c"
#include "watchdog.c" #include "watchdog.c"
#include "southbridge/intel/i82801ex/reset.c" #include "southbridge/intel/i82801ex/reset.c"
#include "superio/winbond/w83627hf/early_serial.c" #include "superio/winbond/w83627hf/early_serial.c"
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7520/memory_initialized.c" #include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>

5
src/mainboard/winent/pl6064/romstage.c
View File

@ -34,7 +34,8 @@
#include <spd.h> #include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c" #include "southbridge/amd/cs5536/early_setup.c"
#include "superio/winbond/w83627hf/early_serial.c" #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -66,7 +67,7 @@ void main(unsigned long bist)
* early MSR setup for CS5536. * early MSR setup for CS5536.
*/ */
w83627hf_set_clksel_48(SERIAL_DEV); w83627hf_set_clksel_48(SERIAL_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */

2
src/superio/winbond/w83627hf/Makefile.inc
View File

@ -20,5 +20,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
romstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += early_init.c
ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.c

37
src/superio/winbond/w83627hf/early_init.c
View File

@ -2,8 +2,9 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2000 AG Electronics Ltd.
* Copyright 2003-2004 Linux Networx * Copyright (C) 2003-2004 Linux Networx
* Copyright 2004 Tyan * Copyright (C) 2004 Tyan
* Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -21,18 +22,34 @@
*/ */
#include <arch/io.h> #include <arch/io.h>
#include <device/pnp.h>
#include "w83627hf.h" #include "w83627hf.h"
void w83627hf_disable_dev(device_t dev) static void pnp_enter_ext_func_mode(device_t dev)
{ {
pnp_set_logical_device(dev); u16 port = dev >> 8;
pnp_set_enable(dev, 0); outb(0x87, port);
outb(0x87, port);
} }
void w83627hf_enable_dev(device_t dev, u16 iobase) static void pnp_exit_ext_func_mode(device_t dev)
{ {
pnp_set_logical_device(dev); u16 port = dev >> 8;
pnp_set_enable(dev, 0); outb(0xaa, port);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase); }
pnp_set_enable(dev, 1);
/*
* We duplicate this function, for non-ROMCC boards, from early_serial.c to
* work around a limitation of ROMCC where we can no make early_serial.c into
* link-time symbols and #include early_serial.c.
*/
void w83627hf_set_clksel_48(device_t dev)
{
u8 reg8;
pnp_enter_ext_func_mode(dev);
reg8 = pnp_read_config(dev, 0x24);
reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
pnp_write_config(dev, 0x24, reg8);
pnp_exit_ext_func_mode(dev);
} }

12
src/superio/winbond/w83627hf/early_serial.c
View File

@ -37,6 +37,18 @@ static void pnp_exit_ext_func_mode(device_t dev)
outb(0xaa, port); outb(0xaa, port);
} }
/*
* FIXME: The following ROMCC boards are blocking the removal this superio's
* model specific w83627hf_enable_serial() symbol.
*
* mainboard/supermicro/x6dai_g
* mainboard/supermicro/x6dhe_g
* mainboard/supermicro/x6dhr_ig
* mainboard/supermicro/x6dhr_ig2
*
* XXX: ROMCC - everything is inlined, no forwarding function prototypes
* declarations are accepted.
*/
void w83627hf_enable_serial(device_t dev, u16 iobase) void w83627hf_enable_serial(device_t dev, u16 iobase)
{ {
pnp_enter_ext_func_mode(dev); pnp_enter_ext_func_mode(dev);

16
src/superio/winbond/w83627hf/w83627hf.h
View File

@ -20,8 +20,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef SUPERIO_WINBOND_W83627HF_W83627HF_H #ifndef SUPERIO_WINBOND_W83627HF_H
#define SUPERIO_WINBOND_W83627HF_W83627HF_H #define SUPERIO_WINBOND_W83627HF_H
#define W83627HF_FDC 0 /* Floppy */ #define W83627HF_FDC 0 /* Floppy */
#define W83627HF_PP 1 /* Parallel port */ #define W83627HF_PP 1 /* Parallel port */
@ -113,11 +113,9 @@
#define W83627HF_XSCNF 0x15 #define W83627HF_XSCNF 0x15
#define W83627HF_XWBCNF 0x16 #define W83627HF_XWBCNF 0x16
#if defined(__PRE_RAM__) #include <arch/io.h>
void w83627hf_disable_dev(device_t dev);
void w83627hf_enable_dev(device_t dev, u16 iobase);
void w83627hf_enable_serial(device_t dev, u16 iobase);
void w83627hf_set_clksel_48(device_t dev);
#endif
#endif void w83627hf_set_clksel_48(device_t dev);
void w83627hf_enable_serial(device_t dev, u16 iobase);
#endif /* SUPERIO_WINBOND_W83627HF_H */