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mb/google/reef: Implement touchscreen power sequencing 

For touchscreens on reef variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit). As the GPIOs are
already correct in ramstage, only the romstage ones need to be set.

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I10d1789c8de23653bac81e1f9604a47f93fa3f7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2022-12-20 16:29:02 -06:00 committed by Martin L Roth
parent 40c8cc9cde
commit beb58a93cf
1 changed files with 9 additions and 2 deletions
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11
src/mainboard/google/reef/variants/baseboard/gpio.c
View File

@ -392,11 +392,18 @@ variant_sleep_gpio_table(u8 slp_typ, size_t *num)
return sleep_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
PAD_CFG_GPO(GPIO_152, 1, DEEP), /* Touch enable */
PAD_CFG_GPO(GPIO_36, 1, DEEP), /* Touch reset */
};
/* Weak implementation of romstage gpio */
const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
*num = 0;
return NULL;
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {