soc/intel/tigerlake: update elog to include CSME reset causes
Call out the CSME-initiated bits from HPR_CAUSE0 register and update the elog to include reset causes Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14 Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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@ -61,6 +61,18 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
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if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
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elog_add_event(ELOG_TYPE_THERM_TRIP);
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/* CSME-Initiated Host Reset with power down */
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if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD)
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elog_add_event(ELOG_TYPE_MI_HRPD);
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/* CSME-Initiated Host Reset with power cycle */
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if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC)
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elog_add_event(ELOG_TYPE_MI_HRPC);
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/* CSME-Initiated Host Reset without power cycle */
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if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR)
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elog_add_event(ELOG_TYPE_MI_HR);
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/* PWR_FLR Power Failure */
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if (ps->gen_pmcon_a & PWR_FLR)
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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