binaryPI: Disable CAR with empty stack
Calling disable_cache_as_ram() with valuables in stack is not a stable solution, as per documentation AMD_DISABLE_STACK should destroy stack in cache. While we still preserve cache contents (there is wbinvd deep inside AMD_DISABLE_STACK macro), we now actually do a stack switch and much more closely meet the specification of CAR teardown sequence in AGESA specifications. We now somewhat incorrectly include files from agesa/ tree, but the whole agesawrapper.c file removal will address the issue of overall directory layout. Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
parent
9de82612fe
commit
bebd766f16
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@ -19,8 +19,9 @@ subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
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romstage-y += romstage.c
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romstage-y += ../agesa/heapmanager.c
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ramstage-y += ../agesa/heapmanager.c
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ramstage-y += amd_late_init.c
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@ -1,170 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/******************************************************************************
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* AMD Generic Encapsulated Software Architecture
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*
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* $Workfile:: cache_as_ram.inc
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*
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* Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
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*
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******************************************************************************
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*/
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#include "gcccar.inc"
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#include <cpu/x86/cache.h>
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/*
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* XMM map:
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* xmm0: BIST
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* xmm1: backup ebx -- cpu_init_detected
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*/
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.code32
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.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
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cache_as_ram_setup:
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post_code(0xa0)
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/* enable SSE2 128bit instructions */
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/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
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movl %cr4, %eax
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orl $(3 << 9), %eax
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movl %eax, %cr4
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/* Get the cpu_init_detected */
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mov $1, %eax
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cpuid
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shr $24, %ebx
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/* Save the BIST result */
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cvtsi2sd %ebp, %xmm0
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/* for normal part %ebx already contain cpu_init_detected from fallback call */
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/* Save the cpu_init_detected */
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cvtsi2sd %ebx, %xmm1
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post_code(0xa1)
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AMD_ENABLE_STACK
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/* Align the stack. */
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and $0xFFFFFFF0, %esp
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#ifdef __x86_64__
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/* switch to 64 bit long mode */
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mov %esi, %ecx
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add $0, %ecx # core number
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xor %eax, %eax
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lea (0x1000+0x23)(%ecx), %edi
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mov %edi, (%ecx)
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mov %eax, 4(%ecx)
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lea 0x1000(%ecx), %edi
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movl $0x000000e3, 0x00(%edi)
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movl %eax, 0x04(%edi)
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movl $0x400000e3, 0x08(%edi)
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movl %eax, 0x0c(%edi)
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movl $0x800000e3, 0x10(%edi)
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movl %eax, 0x14(%edi)
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movl $0xc00000e3, 0x18(%edi)
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movl %eax, 0x1c(%edi)
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# load ROM based identity mapped page tables
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mov %ecx, %eax
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mov %eax, %cr3
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# enable PAE
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mov %cr4, %eax
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bts $5, %eax
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mov %eax, %cr4
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# enable long mode
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mov $0xC0000080, %ecx
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rdmsr
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bts $8, %eax
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wrmsr
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# enable paging
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mov %cr0, %eax
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bts $31, %eax
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mov %eax, %cr0
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# use call far to switch to 64-bit code segment
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ljmp $0x18, $1f
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1:
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/* Pass the cpu_init_detected */
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cvtsd2si %xmm1, %esi
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/* Pass the BIST result */
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cvtsd2si %xmm0, %edi
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.code64
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call cache_as_ram_main
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.code32
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#else
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/* Restore the BIST result */
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cvtsd2si %xmm0, %edx
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/* Restore the cpu_init_detected */
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cvtsd2si %xmm1, %ebx
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/* Must maintain 16-byte stack alignment here. */
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pushl $0x0
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pushl $0x0
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pushl %ebx /* init detected */
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pushl %edx /* bist */
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call cache_as_ram_main
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#endif
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/* Should never see this postcode */
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post_code(0xaf)
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stop:
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jmp stop
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disable_cache_as_ram:
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/* Save return stack */
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movd 0(%esp), %xmm1
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movd %esp, %xmm0
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/* Disable cache */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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AMD_DISABLE_STACK
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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xorl %eax, %eax
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/* Restore the return stack */
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wbinvd
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movd %xmm0, %esp
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movd %xmm1, (%esp)
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ret
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cache_as_ram_setup_out:
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#ifdef __x86_64__
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.code64
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#endif
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@ -0,0 +1,48 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Kyösti Mälkki
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <cpu/amd/car.h>
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#include <cpu/x86/mtrr.h>
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#include <console/console.h>
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#include <program_loading.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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void asmlinkage early_all_cores(void)
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{
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amd_initmmio();
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}
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void * asmlinkage romstage_main(unsigned long bist)
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{
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uintptr_t stack_top = CACHE_TMP_RAMTOP;
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u8 initial_apic_id = cpuid_ebx(1) >> 24;
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/* Only BSP returns from here. */
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cache_as_ram_main(bist, initial_apic_id);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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return (void*)stack_top;
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}
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void asmlinkage romstage_after_car(void)
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{
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printk(BIOS_DEBUG, "CAR disabled.\n");
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agesa_postcar(NULL);
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run_ramstage();
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}
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@ -20,6 +20,7 @@
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/bist.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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@ -28,9 +29,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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hudson_lpc_port80();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -62,18 +60,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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}
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void agesa_postcar(struct sysinfo *cb)
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{
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post_code(0x41);
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AGESAWRAPPER(amdinitenv);
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/* TODO: Disable cache is not ok. */
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disable_cache_as_ram();
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if (acpi_is_wakeup_s4()) {
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outb(0xEE, PM_INDEX);
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outb(0x8, PM_DATA);
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}
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post_code(0x50);
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copy_and_run();
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post_code(0x54); /* Should never see this post code. */
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}
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@ -25,6 +25,7 @@
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <cpu/x86/bist.h>
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@ -32,11 +33,7 @@
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#include <southbridge/amd/pi/hudson/hudson.h>
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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{ u32 val;
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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@ -78,19 +75,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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}
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void agesa_postcar(struct sysinfo *cb)
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{
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post_code(0x41);
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AGESAWRAPPER(amdinitenv);
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/*
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If code hangs here, please check cahaltasm.S
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*/
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disable_cache_as_ram();
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outb(0xEA, 0xCD6);
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outb(0x1, 0xcd7);
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post_code(0x50);
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copy_and_run();
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post_code(0x54); /* Should never see this post code. */
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}
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@ -25,6 +25,7 @@
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <cpu/x86/bist.h>
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@ -40,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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@ -89,16 +87,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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}
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void agesa_postcar(struct sysinfo *cb)
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{
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post_code(0x41);
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AGESAWRAPPER(amdinitenv);
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/*
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If code hangs here, please check cahaltasm.S
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*/
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disable_cache_as_ram();
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post_code(0x50);
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copy_and_run();
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post_code(0x54); /* Should never see this post code. */
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}
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@ -25,6 +25,7 @@
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <cpu/x86/bist.h>
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@ -35,9 +36,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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@ -88,20 +86,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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}
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void agesa_postcar(struct sysinfo *cb)
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{
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//PspMboxBiosCmdDramInfo();
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post_code(0x41);
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AGESAWRAPPER(amdinitenv);
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/*
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If code hangs here, please check cahaltasm.S
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*/
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disable_cache_as_ram();
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outb(0xEA, 0xCD6);
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outb(0x1, 0xcd7);
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post_code(0x50);
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copy_and_run();
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post_code(0x54); /* Should never see this post code. */
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}
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@ -25,6 +25,7 @@
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <cpu/x86/bist.h>
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@ -39,9 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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@ -82,20 +80,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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}
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void agesa_postcar(struct sysinfo *cb)
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{
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//PspMboxBiosCmdDramInfo();
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post_code(0x41);
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AGESAWRAPPER(amdinitenv);
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/*
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If code hangs here, please check cahaltasm.S
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*/
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disable_cache_as_ram();
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outb(0xEA, 0xCD6);
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outb(0x1, 0xcd7);
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post_code(0x50);
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copy_and_run();
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post_code(0x54); /* Should never see this post code. */
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}
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@ -25,6 +25,7 @@
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <cpu/x86/bist.h>
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@ -52,8 +53,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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outb(0xD2, 0xcd6);
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outb(0x00, 0xcd7);
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amd_initmmio();
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hudson_lpc_port80();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -85,27 +84,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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}
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void agesa_postcar(struct sysinfo *cb)
|
||||
{
|
||||
//PspMboxBiosCmdDramInfo();
|
||||
post_code(0x41);
|
||||
AGESAWRAPPER(amdinitenv);
|
||||
/*
|
||||
If code hangs here, please check cahaltasm.S
|
||||
*/
|
||||
disable_cache_as_ram();
|
||||
|
||||
init_tpm(false);
|
||||
|
||||
outb(0xEA, 0xCD6);
|
||||
outb(0x1, 0xcd7);
|
||||
|
||||
post_code(0x50);
|
||||
copy_and_run();
|
||||
|
||||
post_code(0x54); /* Should never see this post code. */
|
||||
}
|
||||
|
||||
|
||||
static void early_lpc_init(void)
|
||||
{
|
||||
u32 setting = 0x0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue