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mb/intel/glkrvp: Configure SCI/SMI in glkrvp for ESPI 

This patch configures the EC_SCI_GPI when ESPI is enabled.Also adds
mainboard espi handler function.

TEST= Boot to OS and SMI/SCI is working when ESPI is enabled/disabled.

Change-Id: I2b3845d54ad7c1f14edc86f71b3f968424711999
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2017-12-06 12:23:01 -08:00 committed by Martin Roth
parent 41cfd5ba69
commit bebec08ca0
2 changed files with 9 additions and 0 deletions
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5
src/mainboard/intel/glkrvp/smihandler.c
View File

@ -50,3 +50,8 @@ int mainboard_smi_apmc(u8 apmc)
MAINBOARD_EC_SMI_EVENTS); MAINBOARD_EC_SMI_EVENTS);
return 0; return 0;
} }
void mainboard_smi_espi_handler(void)
{
chromeec_smi_process_events();
}

4
src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
View File

@ -22,7 +22,11 @@
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
* which is North community * which is North community
*/ */
#if IS_ENABLED(CONFIG_SOC_ESPI)
#define EC_SCI_GPI GPE0A_ESPI_SCI_STS
#else
#define EC_SCI_GPI GPE0_DW1_05 #define EC_SCI_GPI GPE0_DW1_05
#endif
/* EC SMI */ /* EC SMI */
#define EC_SMI_GPI GPIO_41 #define EC_SMI_GPI GPIO_41