amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c
In preparation to deleting early_setup,c, transfer all functions except those related to wide IO to southbridge.c. BUG=b:64033893 TEST=Build and boot to OS. Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Richard Spiegel
Martin Roth
parent
61c817d0af
commit
bec44f22a4
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@ -45,6 +45,7 @@ bootblock-y += pmutil.c
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bootblock-y += reset.c
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bootblock-y += sb_util.c
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bootblock-y += tsc_freq.c
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bootblock-y += southbridge.c
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romstage-y += BiosCallOuts.c
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romstage-y += romstage.c
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@ -60,6 +61,7 @@ romstage-y += smbus_spd.c
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romstage-y += ramtop.c
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romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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romstage-y += tsc_freq.c
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romstage-y += southbridge.c
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verstage-y += sb_util.c
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verstage-y += pmutil.c
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@ -27,98 +27,6 @@
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#include <cpu/x86/msr.h>
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#include <delay.h>
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void configure_stoneyridge_uart(void)
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{
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u8 byte, byte2;
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if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)
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return;
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/* Power on the UART and AMBA devices */
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byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
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+ CONFIG_UART_FOR_CONSOLE * 2);
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byte |= AOAC_PWR_ON_DEV;
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write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
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+ CONFIG_UART_FOR_CONSOLE * 2, byte);
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byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62);
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byte |= AOAC_PWR_ON_DEV;
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write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte);
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/* Set the GPIO mux to UART */
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write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
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write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
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write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
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write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
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/* Wait for the UART and AMBA devices to indicate power and clock OK */
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do {
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udelay(100);
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byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57
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+ CONFIG_UART_FOR_CONSOLE * 2);
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byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
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byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE
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+ FCH_AOAC_REG63);
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byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
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} while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) &&
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(byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))));
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}
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void sb_pci_port80(void)
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{
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u8 byte;
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pci_devfn_t dev;
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dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
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byte = pci_read_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH);
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byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */
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pci_write_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
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}
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void sb_lpc_port80(void)
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{
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u8 byte;
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pci_devfn_t dev;
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/* Enable LPC controller */
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outb(PM_LPC_GATING, PM_INDEX);
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byte = inb(PM_DATA);
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byte |= PM_LPC_ENABLE;
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outb(PM_LPC_GATING, PM_INDEX);
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outb(byte, PM_DATA);
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/* Enable port 80 LPC decode in pci function 3 configuration space. */
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dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
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byte = pci_read_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH);
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byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */
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pci_write_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
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}
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void sb_lpc_decode(void)
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{
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pci_devfn_t dev;
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u32 tmp = 0;
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/* Enable I/O decode to LPC bus */
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dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
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tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
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| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
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| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
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| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
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| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
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| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
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| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
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| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
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| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
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| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
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| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
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| DECODE_ENABLE_ADLIB_PORT;
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pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
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}
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static void enable_wideio(uint8_t port, uint16_t size)
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{
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uint32_t wideio_enable[] = {
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@ -205,169 +113,3 @@ void lpc_wideio_16_window(uint16_t base)
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assert(IS_ALIGNED(base, 16));
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lpc_wideio_window(base, 16);
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}
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int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
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{
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int i;
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printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n",
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dword, size, nvram_pos);
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for (i = 0; i < size; i++) {
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outb(nvram_pos, BIOSRAM_INDEX);
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outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
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nvram_pos++;
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}
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return nvram_pos;
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}
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int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
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{
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u32 data = *old_dword;
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int i;
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for (i = 0; i < size; i++) {
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outb(nvram_pos, BIOSRAM_INDEX);
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data &= ~(0xff << (i * 8));
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data |= inb(BIOSRAM_DATA) << (i * 8);
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nvram_pos++;
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}
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*old_dword = data;
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printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n",
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*old_dword, size, nvram_pos-size);
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return nvram_pos;
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}
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void sb_clk_output_48Mhz(void)
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{
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u32 ctrl;
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/*
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* Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
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* 48Mhz will be on ball AP13 (FT3b package)
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*/
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ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));
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/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
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ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN;
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write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
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}
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static uintptr_t sb_spibase(void)
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{
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/* Make sure the base address is predictable */
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device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
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u32 base, enables;
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base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
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enables = base & 0xf;
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base &= ~0x3f;
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if (!base) {
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base = SPI_BASE_ADDRESS;
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pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base
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| enables | SPI_ROM_ENABLE);
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/* PCI_COMMAND_MEMORY is read-only and enabled. */
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}
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return (uintptr_t)base;
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}
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void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
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{
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uintptr_t base = sb_spibase();
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write16((void *)base + SPI100_SPEED_CONFIG,
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(norm << SPI_NORM_SPEED_NEW_SH) |
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(fast << SPI_FAST_SPEED_NEW_SH) |
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(alt << SPI_ALT_SPEED_NEW_SH) |
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(tpm << SPI_TPM_SPEED_NEW_SH));
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write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100);
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}
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void sb_disable_4dw_burst(void)
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{
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uintptr_t base = sb_spibase();
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write16((void *)base + SPI100_HOST_PREF_CONFIG,
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read16((void *)base + SPI100_HOST_PREF_CONFIG)
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& ~SPI_RD4DW_EN_HOST);
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}
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void sb_set_readspeed(u16 norm, u16 fast)
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{
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uintptr_t base = sb_spibase();
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write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1)
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& ~SPI_CNTRL1_SPEED_MASK)
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| (norm << SPI_NORM_SPEED_SH)
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| (fast << SPI_FAST_SPEED_SH));
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}
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void sb_read_mode(u32 mode)
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{
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uintptr_t base = sb_spibase();
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write32((void *)base + SPI_CNTRL0,
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(read32((void *)base + SPI_CNTRL0)
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& ~SPI_READ_MODE_MASK) | mode);
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}
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void sb_tpm_decode_spi(void)
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{
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device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */
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u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
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pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
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| ROUTE_TPM_2_SPI);
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}
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/*
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* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
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*
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* Hardware should enable LPC ROM by pin straps. This function does not
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* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
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*
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* The southbridge power-on default is to map 512K ROM space.
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*
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*/
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void sb_enable_rom(void)
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{
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u8 reg8;
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pci_devfn_t dev;
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dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
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/*
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* Decode variable LPC ROM address ranges 1 and 2.
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* Bits 3-4 are not defined in any publicly available datasheet
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*/
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reg8 = pci_io_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
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reg8 |= (1 << 3) | (1 << 4);
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pci_io_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg8);
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/*
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* LPC ROM address range 1:
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* Enable LPC ROM range mirroring start at 0x000e(0000).
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*/
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pci_io_write_config16(dev, ROM_ADDRESS_RANGE1_START, 0x000e);
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/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
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pci_io_write_config16(dev, ROM_ADDRESS_RANGE1_END, 0x000f);
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/*
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* LPC ROM address range 2:
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*
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* Enable LPC ROM range start at:
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* 0xfff8(0000): 512KB
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* 0xfff0(0000): 1MB
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* 0xffe0(0000): 2MB
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* 0xffc0(0000): 4MB
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*/
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pci_io_write_config16(dev, ROM_ADDRESS_RANGE2_START, 0x10000
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- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
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/* Enable LPC ROM range end at 0xffff(ffff). */
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pci_io_write_config16(dev, ROM_ADDRESS_RANGE2_END, 0xffff);
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}
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void bootblock_fch_early_init(void)
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{
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sb_enable_rom();
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sb_lpc_port80();
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sb_lpc_decode();
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}
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@ -28,7 +28,254 @@
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#include <soc/southbridge.h>
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#include <soc/smi.h>
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#include <fchec.h>
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#include <delay.h>
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#include <soc/pci_devs.h>
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void configure_stoneyridge_uart(void)
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{
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u8 byte, byte2;
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if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)
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return;
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/* Power on the UART and AMBA devices */
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byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
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+ CONFIG_UART_FOR_CONSOLE * 2);
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byte |= AOAC_PWR_ON_DEV;
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write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
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+ CONFIG_UART_FOR_CONSOLE * 2, byte);
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byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62);
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byte |= AOAC_PWR_ON_DEV;
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write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte);
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/* Set the GPIO mux to UART */
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write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
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write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
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write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
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write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
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/* Wait for the UART and AMBA devices to indicate power and clock OK */
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do {
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udelay(100);
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byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57
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+ CONFIG_UART_FOR_CONSOLE * 2);
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byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
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byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE
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+ FCH_AOAC_REG63);
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byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
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} while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) &&
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(byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))));
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}
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void sb_pci_port80(void)
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{
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u8 byte;
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byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
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byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */
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pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
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}
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void sb_lpc_port80(void)
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{
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u8 byte;
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/* Enable LPC controller */
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outb(PM_LPC_GATING, PM_INDEX);
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byte = inb(PM_DATA);
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byte |= PM_LPC_ENABLE;
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outb(PM_LPC_GATING, PM_INDEX);
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outb(byte, PM_DATA);
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/* Enable port 80 LPC decode in pci function 3 configuration space. */
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byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
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byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */
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pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
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}
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void sb_lpc_decode(void)
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{
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u32 tmp = 0;
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/* Enable I/O decode to LPC bus */
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tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
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| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
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| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
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| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
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| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
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| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
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| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
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| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
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| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
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| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
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| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
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| DECODE_ENABLE_ADLIB_PORT;
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pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp);
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}
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void sb_clk_output_48Mhz(void)
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{
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u32 ctrl;
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/*
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* Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
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* 48Mhz will be on ball AP13 (FT3b package)
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*/
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ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));
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/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
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ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN;
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write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
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}
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static uintptr_t sb_spibase(void)
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||||
{
|
||||
u32 base, enables;
|
||||
|
||||
/* Make sure the base address is predictable */
|
||||
base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
|
||||
enables = base & 0xf;
|
||||
base &= ~0x3f;
|
||||
|
||||
if (!base) {
|
||||
base = SPI_BASE_ADDRESS;
|
||||
pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER,
|
||||
base | enables | SPI_ROM_ENABLE);
|
||||
/* PCI_COMMAND_MEMORY is read-only and enabled. */
|
||||
}
|
||||
return (uintptr_t)base;
|
||||
}
|
||||
|
||||
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
|
||||
{
|
||||
uintptr_t base = sb_spibase();
|
||||
write16((void *)base + SPI100_SPEED_CONFIG,
|
||||
(norm << SPI_NORM_SPEED_NEW_SH) |
|
||||
(fast << SPI_FAST_SPEED_NEW_SH) |
|
||||
(alt << SPI_ALT_SPEED_NEW_SH) |
|
||||
(tpm << SPI_TPM_SPEED_NEW_SH));
|
||||
write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100);
|
||||
}
|
||||
|
||||
void sb_disable_4dw_burst(void)
|
||||
{
|
||||
uintptr_t base = sb_spibase();
|
||||
write16((void *)base + SPI100_HOST_PREF_CONFIG,
|
||||
read16((void *)base + SPI100_HOST_PREF_CONFIG)
|
||||
& ~SPI_RD4DW_EN_HOST);
|
||||
}
|
||||
|
||||
void sb_set_readspeed(u16 norm, u16 fast)
|
||||
{
|
||||
uintptr_t base = sb_spibase();
|
||||
write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1)
|
||||
& ~SPI_CNTRL1_SPEED_MASK)
|
||||
| (norm << SPI_NORM_SPEED_SH)
|
||||
| (fast << SPI_FAST_SPEED_SH));
|
||||
}
|
||||
|
||||
void sb_read_mode(u32 mode)
|
||||
{
|
||||
uintptr_t base = sb_spibase();
|
||||
write32((void *)base + SPI_CNTRL0,
|
||||
(read32((void *)base + SPI_CNTRL0)
|
||||
& ~SPI_READ_MODE_MASK) | mode);
|
||||
}
|
||||
|
||||
void sb_tpm_decode_spi(void)
|
||||
{
|
||||
u32 spibase = pci_read_config32(SOC_LPC_DEV,
|
||||
SPIROM_BASE_ADDRESS_REGISTER);
|
||||
pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase
|
||||
| ROUTE_TPM_2_SPI);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
|
||||
*
|
||||
* Hardware should enable LPC ROM by pin straps. This function does not
|
||||
* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
|
||||
*
|
||||
* The southbridge power-on default is to map 512K ROM space.
|
||||
*
|
||||
*/
|
||||
void sb_enable_rom(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
/*
|
||||
* Decode variable LPC ROM address ranges 1 and 2.
|
||||
* Bits 3-4 are not defined in any publicly available datasheet
|
||||
*/
|
||||
reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
|
||||
reg8 |= (1 << 3) | (1 << 4);
|
||||
pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8);
|
||||
|
||||
/*
|
||||
* LPC ROM address range 1:
|
||||
* Enable LPC ROM range mirroring start at 0x000e(0000).
|
||||
*/
|
||||
pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e);
|
||||
|
||||
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
|
||||
pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f);
|
||||
|
||||
/*
|
||||
* LPC ROM address range 2:
|
||||
*
|
||||
* Enable LPC ROM range start at:
|
||||
* 0xfff8(0000): 512KB
|
||||
* 0xfff0(0000): 1MB
|
||||
* 0xffe0(0000): 2MB
|
||||
* 0xffc0(0000): 4MB
|
||||
*/
|
||||
pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
|
||||
- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
|
||||
|
||||
/* Enable LPC ROM range end at 0xffff(ffff). */
|
||||
pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
|
||||
}
|
||||
|
||||
void bootblock_fch_early_init(void)
|
||||
{
|
||||
sb_enable_rom();
|
||||
sb_lpc_port80();
|
||||
sb_lpc_decode();
|
||||
}
|
||||
|
||||
int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
|
||||
{
|
||||
int i;
|
||||
printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n",
|
||||
dword, size, nvram_pos);
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
outb(nvram_pos, BIOSRAM_INDEX);
|
||||
outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
|
||||
nvram_pos++;
|
||||
}
|
||||
|
||||
return nvram_pos;
|
||||
}
|
||||
|
||||
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
|
||||
{
|
||||
u32 data = *old_dword;
|
||||
int i;
|
||||
for (i = 0; i < size; i++) {
|
||||
outb(nvram_pos, BIOSRAM_INDEX);
|
||||
data &= ~(0xff << (i * 8));
|
||||
data |= inb(BIOSRAM_DATA) << (i * 8);
|
||||
nvram_pos++;
|
||||
}
|
||||
*old_dword = data;
|
||||
printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n",
|
||||
*old_dword, size, nvram_pos-size);
|
||||
return nvram_pos;
|
||||
}
|
||||
|
||||
int acpi_get_sleep_type(void)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue