Define RAMTOP for x86 only

This Kconfig is deprecated, new platforms need to locate
ramstage stack in CBMEM instead.

Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15189
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2016-06-15 02:25:00 +03:00
parent e51c20bf2c
commit bec853e9ad
5 changed files with 5 additions and 19 deletions

View File

@ -469,11 +469,6 @@ config TPM
If unsure, say N.
config RAMTOP
hex
default 0x200000
depends on ARCH_X86
config HEAP_SIZE
hex
default 0x4000

View File

@ -83,6 +83,11 @@ config RAMBASE
hex
default 0x100000
config RAMTOP
hex
default 0x200000
depends on ARCH_X86
# Traditionally BIOS region on SPI flash boot media was memory mapped right below
# 4G and it was the last region in the IFD. This way translation between CPU
# address space to flash address was trivial. However some IFDs on newer SoCs

View File

@ -44,10 +44,4 @@ config DRAM_SIZE_MB
int
default 32768
# Memory map for qemu power8
config RAMTOP
hex
default 0x1000000
endif # BOARD_EMULATION_QEMU_POWER8

View File

@ -54,8 +54,4 @@ config DRAM_SIZE_MB
# 0x0011_0000: CBFS data
# 0x0100_0000: reserved for ramstage
config RAMTOP
hex
default 0x1000000
endif # BOARD_EMULATION_QEMU_UCB_RISCV

View File

@ -54,8 +54,4 @@ config DRAM_SIZE_MB
# 0x0011_0000: CBFS data
# 0x0100_0000: reserved for ramstage
config RAMTOP
hex
default 0x1000000
endif # BOARD_EMULATION_SPIKE_UCB_RISCV